Current postgraduate taught students
COMP70042: Low-Power System Design (2007-2008)
The aim of this course is to introduce students to the practical aspects of engineering high-performance computer systems where power consumption is a major consideration at every stage of the design. The course is heavily based around the ARM 32-bit RISC microprocessor, a world-leading processor for power-sensitive applications, and covers many aspects of designing power-efficient systems around ARM cores
A student completing this course unit should have achieved:
an understanding of the principles of the ARM and Thumb instruction sets and their practical use.
an understanding of the principles of low-power RISC processor design.
an insight into the design of memory hierarchies for power-efficient systems, and an ability to apply a systematic methodology to memory hierarchy design
an overview of the system-level issues involved in designing a particular power-sensitive application (a GSM digital mobile phone handset).
a preliminary view of the potential role of asynchronous design in future low-power systems.
an ability to write clear and concise reports on matters relating to low-power design.
Assessment of Learning outcomes100% assessed excercises. Assignments (typical):
Assignment 1 is concerned with the analysis of cache memory behaviour.
Assignment 2 is concerned with the analysis and optimisation of a representative low power application program.
Computing is becoming increasingly mobile, both in recognisable forms such as lap-top computers and in forms where the computing function is concealed such as digital mobile telephones. Mobile computing increases significantly the importance of minimising the power consumed by the system as excessive consumption directly compromises battery life.
ARM assembly language programming
ARM software development tools; the ARM programmers' model; the ARM instruction set; writing simple programs; example programs
Support for high-level languages
ARM data types; memory organization; high-level language support.
The ARM instruction set in detail
Operating modes and exceptions; conditional execution; instruction types and functions.
The Thumb instruction set
The Thumb programmers' model; Thumb instructions; Thumb implementation; Thumb applications; example Thumb programs.
ARM integer cores
ARM organization; the ARM 3- and 5-stage pipelines; the ARM7TDMI core; the ARM9TDMI core.
The ARM coprocessor interface; floating-point support; DSP support.
On-chip RAM; caches; memory management; operating systems; the ARM system control coprocessor; the ARM MMU architecture; the ARM memory protection unit.
The ARM700 series; the ARM810; StrongARM; the ARM900 series; the ARM1020
The ARMulator; JTAG test access port; embedded core debug; embedded trace; the AMBA on-chip bus; hardware prototyping; examples of embedded system chips.
Case study - a GSM handset
The GSM digital cellular network; handset organisation; hardware/software trade-offs; power minimisation.
Asynchronous design for low power
Motivation for asynchronous design; asynchronous design styles; micropipelines.
The AMULET microprocessors
AMULET1 organisation; AMULET1 characteristics; lessons from AMULET1; the AMULET2e asynchronous embedded controller; the AMULET3H SoC subsystem; the DRACO chip.
Full course notes, including the laboratory manual, will be supplied as work packages in Text and/or PDF format.
Fully on-line distance learning with on-line support.
10 hours of on-line tutorials.
Bulletin boards on-line.
Work package documents supplied on-line.
Course material course notes and CBT package supplied on-line.
Course book paper based.
Core TextTitle: ARM system-on-chip architecture (2nd edition)
Author: Furber, Steve
Publisher: Addison Wesley