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Current postgraduate taught students

COMP70212: Self Timed Logic (Asynchronous Design) (2007-2008)

This is an archived syllabus from 2007-2008

Self Timed Logic (Asynchronous Design)
Level: 7
Credit rating: 15
Pre-requisites: Some background in digital design is assumed. In particular it is assumed. Concepts such as logic gates. Flip-flops and Boolean logic are familiar.
Co-requisites: No Co-requisites
Lectures: 8 - 10 hours.
Course lecturer: not assignedAdditional staff: view all staff
Assessment Breakdown
Exam: 0%
Coursework: 0%
Lab: 0%

Introduction

This course has been developed to give an understanding of the approaches required so that the designer is able to establish when it may be advantageous to use asynchronous techniques to solve a design problem.

Aims

On completion of this unit successful students will be able to:
demonstrate an awareness of the potential advantages of asynchronous systems.
understand asynchronous data and control protocols.
be aware of asynchronous synthesis tools.
show familiarity with the latest results from research into asynchronous systems.
demonstrate an ability to write clear and concise reports on matters relating to asynchronous design.

Syllabus

Introduction



Why consider asynchronous circuits, aims and background, clocking versus handshaking.

Fundamentals


Handshake protocols, the Muller pipeline, delay models.


Static data-flow structures


Pipelines and rings, building blocks, example GCD.

Performance


A qualitative view of performance, quantifying performance, dependency graph analysis.


Handshake circuit implementations


The latch, Fork, join and merge, function blocks, mutual exclusion, arbitration and metastability.


Speed-independent control circuits


Signal transition graphs, synthesis procedure, Petrify, design examples using Petrify.

VLSI programming



Handshake circuits. an asynchronous HDL - Balsa. Using Balsa to describe circuits (buffers, stacks, recursive and parameterised structures).

An introduction to Amulet processors


Processor implemetation techniques, memory organization, asynchronous on-chip interconnect.

Reading List

Delivery Mode:
Fully on-line distance learning with on-line support.
10 hours of on-line tutorials.
Bulletin boards on-line.
Work package documents supplied on-line.
Course material course notes and CBT package supplied on-line.
On-line examination.
Course book paper based.http://intranet.cs.man.ac.uk/peve/

Core Text
Title: Principles of asynchronous circuit design: a systems perspective (European low power initiative for electronic system design) A Systems Perspective
Author: Sparso, Jens and Steve Furber (eds.). Sparsx, Jens
ISBN: 0792376137
Publisher: Kluwer Academic Publishers Group
Edition: Sparsx, Jens
Year: 2002