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This is an archived syllabus from 2013-2014

COMP60621 Designing for Parallelism and Future Multi-core Computing syllabus 2013-2014

COMP60621 Designing for Parallelism and Future Multi-core Computing

Level 6
Credits: 15
Enrolled students: 17

Course leader: Mikel Lujan

Additional staff: view all staff

Assessment methods

  • 50% Written exam
  • 50% Coursework
Sem 1 P2 Lecture 2.15 Thu 09:00 - 09:00 -
Themes to which this unit belongs
  • Parallel Computing in the Multi-core Era


Dual-core and Quad-core processors are now becoming commonplace as circuit limits are reached which prevent further performance gains from simple clock-speed increases. Major industrial projections expect processors with hundreds of cores within a few years. But, current hardware architectural approaches are not applicable to the scale of these future processors. In addition, programming techniques, required to write general purpose parallel programs to make effective use of these systems, are regarded as inadequate. These are therefore very active research areas and there are a number of different but inter-related directions being explored. The purpose of this course unit is to study that research by a combination of directed reading and practical experimentation with state-of-the art multi-core hardware, simulators of research systems and novel language implementations.


The unit aims to study the technological issues which will determine both the future hardware architecture and the programming techniques which will be necessary to extract performance from multi-core processors. It will examine the limitations of current approaches and study in detail those areas of research which are most likely to provide solutions.

Learning and Teaching Processes

Introductory material will be provided by a small number of traditional lectures. The majority of the research material will be covered by directed reading followed by small group presentation and discussion. Practical work will take the form of small group projects where a student will be expected to investigate a particular topic in depth by experiment.

Feedback methods

Informal feedback during the course, plus one-to-one dedicated time to provide feedback on the lab exercises and how to improve answers for the exam

Study hours

  • Lectures (35 hours)

Employability skills

  • Analytical skills
  • Group/team working
  • Innovation/creativity
  • Leadership
  • Oral communication
  • Problem solving
  • Research
  • Written communication

Learning outcomes

Programme outcomeUnit learning outcomesAssessment
G1Understand the limitations of current multi-core computing. Have detailed knowledge of those areas of research that are intended to address both the hardware architecture and programming approaches which will be needed to develop future high performance multi-core systems.
G1 G2Be able to analyse current research in the multi-core area with the ability to judge whether they are promising in the context of the technological limitations which constrain progress.
G1 G2 G3Be able to access the parallel potential of multi-core systems both by the use of real hardware and simulation. Be able to develop parallel programs for multi-core systems using novel programming approaches.
G2 G3 G4Be able to evaluate research by literature study. Be able to perform research level presentations. Small group working skills.

Reading list

Computer architecture: a quantitative approach (5th edition)Hennessy, John L. and David A. Patterson9780123838728Morgan Kaufmann2011
Principles and practices of interconnection networksDally, William James and Brian Patrick Towles9780122007514Morgan Kaufmann2004
Art of multiprocessor programming (revised 1st edition)Herlihy, Maurice and Nir Shavit9780123973375Morgan Kaufmann2012
On-chip networksJerger, Natalie D. Enright and Li-Shiuan Peh9781598295849Morgan & Claypool2009
On-chip communication architectures: system on chip interconnectPasricha, Sudeep and Nikil Dutt9780123738929Morgan Kaufmann2008
Computer architecture techniques for power-efficiencyKaxiras, Stefanos and Margaret Martonosi9781598292084Morgan & Claypool2008
Memory system: you can't avoid it, you can't ignore it, you can't fake itJacob, Bruce9781598295870Morgan & Claypool2008
Memory systems: cache, DRAM, diskJacob, Bruce and Spencer W. Ng and David T. Wang9780123797513Morgan Kaufmann2008
Java concurrency in practiceGoetz, Brian et al9780321349606Addison Wesley2015
Transactional memory (2nd edition)Harris, Tim and James Larus and Raji Rajwar9781608452354Morgan & Claypool2010

Additional notes

Course unit materials

Links to course unit teaching materials can be found on the School of Computer Science website for current students.