AT91SAM9261 The AT91SAM9261 contains an ARM9 (ARM926EJ-S) core with 16KB each of instruction and data cache. The processor is capable of running at up to 240MHz; the exact speed is programmed via an on-board PLL. There is 160KB of memory-mapped SRAM on the microcontroller. The AT91SAM9261 has 96 I/O pins. These are organised as three 32-bit ports - designated {A, B, C} and can be controlled via a PIO. In addition every I/O pin has one or (usually) two specialist alternative functions. These alternative functions have been considered when assigning functions to pins. All I/O pins are supplied from the 3.3V power plane. At reset all I/O pins are inputs and have a 100K pull up resistor enabled. A small number of pins have other passive biases applied, as described below. Ports A and B are pinned out in groups of 16 signals. In normal operation these are typically uncommitted but there are some particular features which may prove useful: PA0-3 can form an SPI bus: this can be used to bootstrap a `blank' board with the appropriate boot mode setting (for example from a plug-in boot module). It could also be used for peripheral control. PA7-8 can act as an I2C port. PA9-10 act as the serial debug port which - with the appropriate boot mode and in the absence of a response on the SPI bus - can be used to bootstrap the system. These pins are pinned out at 3.3V so a plug-in board with a MAX2323 and a connector is suggested for host connection. PB2 can carry a programmable clock. PB3 also acts as `BMS' which controls whether the microcontroller boots from internal or external ROM. As the normal option is external ROM this pin is normally pulled low through a 10K resistor. A link, added after bootstrap programming, makes this connection; if not fitted the internal 100K pull up will cause an internal ROM boot. In use, if left floating, this signal therefore appears different from the other I/O bits. BMS is only sampled on reset so the pin can be used normally. PB29 can double as an interrupt input. PB30 is also led to the FPGA. This pin can double as an interrupt input. PB31 can carry a programmable clock. This pin is also wired to a clock input on the FPGA; this allows the FPGA to be clocked if the 32-bit data bus option is selected (and PC31/PCK1 is therefore in use). An external 50MHz oscillator is connectable to this pin via a link. Port C is used for on-board I/O and other communication. Several options for system configuration are catered for. PC0-1 are dedicated as PROG_B and CCLK and are used for resetting and programming the FPGA. These signals will be pulled high by the AT91's internal 100K pull-ups until the port is driven. (ProgB is active low.) PC2 is connected to an I/O pin on the FPGA. If desired it can form an interrupt (IRQ0) to the ARM. Alternatively it can be used as `NWAIT' - the EBI's wait signal; this could be useful if the bus is extended, via the FPGA, to encompass slow peripherals. PC3 is the enable to the on-board LCD module (LCD_E). [The other LCD control signals are attached to PC16 (LCD_RS) and PC17 (LCD_RW).] This signal is also connected to an I/O pin on the FPGA. A 10K pull down keeps the LCD disabled if the AT91/FPGA are not programmed. PC4-5 are inputs from on-board push switches. These signals are also connected to FPGA I/Os. It is assumed that the AT91's internal (100K) pull-up will be used to pull the signal high. When pressed the switches pull the signals low via a 10K resistor (which prevents the track being accidentally shorted to ground if the signal is driven). These signals can be driven as AT91/FPGA comms. lines if necessary. *1 PC6 is the LED enable; this can tristate the buffer driving the LEDs. It is active low. On reset the internal pull up will extinguish the LEDs. This signal is not attached to the FPGA. PC7 controls the LCD backlight. It is active high. On reset the internal pull up would illuminate the LCD until programmed otherwise; a 10K pull-down resistor prevents this. PC8-9 are dedicated to the primary serial port. They are buffered to/from RS232 levels. Alternatively they can be used as I/O bits to act as (buffered) RTS/CTS (respectively) on the secondary I/O port. PC10 is connected to an I/O pin on the FPGA. If desired it can be used to supply a baud rate clock from UART0. PC11 is connected to an I/O pin on the FPGA. If desired it can be used as the FIQ input for the processor. A third button is also connected in the same manner as PC4-5. *1 PC12-13 are dedicated to the secondary serial port. They are buffered to/from RS232 levels. PC14-15 are used to support the USB device interface. PC14 needs to be driven low to enable the pull-up on the USB line. PC15 should be an input which senses the presence of a USB host connection (i.e. power supply). These bits are also brought out to a header together with Vdd & Vss so that their secondary function (as a serial port) can be used if the USB is not in use. This requires an external buffer if RS232 levels are required. PC14-15 are brought out to a header together with Vdd & Vss so that their secondary function (as a serial port) can be used. This requires an external buffer if RS232 levels are required. Normally PC15 should be an input which senses the presence of a USB host connection (i.e. power supply). [On the first prototype - before it was documented that an internal pull-up existed - PC14 enabled the pull-up on the USB device interface.] PC16-31 are connected to the FPGA. These pins can be used as the upper 32 bits of the ARM's data bus, so that it is possible to programme a 32-bit interface to the FPGA if desired. A subset of these bits is used (under software control) to programme the FPGA. PC16-19 are wired to the FPGA's dual function pins CS_B, RDWR_B, Init_B and Busy respectively; PC23-30 form the data bus to the FPGA's data port. (See also the dedicated functions on PC0-1.) PC16 also doubles as the LCD module address line (LCD_RS). PC17 also doubles as direction control for the LCD module (LCD_RW). PC20, PC21, PC22 and PC31 are wired to (potential) clock inputs on the FPGA. These signals can be programmed to output programmable clocks from the one of the microcontroller's timers (TIOB0, TIOA1, TIOB1) and clock generators (PCK1) respectively. Alternatively they can be used for general I/O. PC23-30 are also used as a general, software controllable, I/O bus to drive the on-board `traffic light' LEDs and the data bus for a character LCD. If floated - such as on start up - PC23-26 are biased to digital levels via resistors and DIP switches. This allows the selection from one of a number of different applications to be run. On board memory There is an 8Mbyte Flash memory attached to NCS0 of the microcontroller: this is usually used to boot the system. There is no external RAM connected directly to the microcontroller; there is 1Mbyte of SRAM accessible via the FPGA. Startup At boot, software in the on-board Flash ROM will float and read the input bits PC22-25 which are biased to levels via DIP switches. This controls the application which is run. By adding a link it is possible to alter the bias of the BMS pin and boot from an external source (as described in the device datasheet). The options are: ROM on SPI bus USB device port Debug serial line The USB is available directly. The SPI and debug port are available via a plug-in on the appropriate port A expansion connector. An external boot is required the first time a board is powered on. It is envisaged that this will programme the Flash with its own downloader. Typical example configuration. A normal configuration would be as follows: AT91 ports A and B would be set as uncommitted I/O on expansion connectors (64 signals). There are options on certain signals which can provide: One or two SPI buses An I2C interface A (limited function) 3V3 serial line One or two programmable clocks One or two interrupt inputs AT91 port C would provide the load interface for the FPGA. Two lines are dedicated to the load control; up to 22 further signals may be used as a software controlled FPGA interface, although some are shared with other devices. Typically an 8-bit `bus' will be used to load the FPGA, communicate with the LCD and will be displayed on the LEDs. Push buttons bias three of the lines if they are floated. Other bits which may be programmed into the interface are: nWAIT/IRQ0 to the AT91 FIQ input to the AT91 SCK0 - a baud clock PCK1 - a programmable clock In addition, two bits from port B reach the FPGA (in addition to an expansion connector. These can be reprogrammed to provide: IRQ1 to the AT91 and PCK2 - a programmable clock Port C bits also (uniquely) control the LCD backlight and global LED enable. Two serial ports {TxD/RxD} are buffered to RS232 compatible levels. A USB host port and USB device port are supported. The FPGA interface would be via the processor's bus; typically 16 bits wide. Seven address lines and two chip selects allow the mapping of 256 byte locations; various read and write and byte strobe combinations are provided for. By reprogramming, the additional signals may be provided: another 16 data bits one or two more chip selects nWAIT (normally AT91 internally programmed timing would be used) clock signals can be supplied to the FPGA via PC10 (SCK0), PC20 (TIOB0), PC21 (TIOA1), PC22 (TIOB1) and PC31 (PCK1), all of which can be connected to the FPGA's clock networks. By `arrangement' with the AT91 the FPGA can have mastery of the 8 LEDs or the character LCD. (It is suggested that one `unused' I/O line from the microcontroller to the FPGA is dedicated as an FPGA data output enable to prevent the FPGA from driving the I/O lines if the microcontroller needs to. [This may be most relevant for FPGA reconfiguration.]) The FPGA can sense the on-board push buttons. The two 512K RAMs have a dedicated bus, private to the FPGA. 64 uncommitted I/O signals are available on expansion connectors. Another 16 are also available but are shared with the private RAM data bus, thus have limited function or prevent one of the local RAMs from being used. Spartan 3 FPGA (XC3S200-FT256) The target FPGA is the XC3S200-FT256 (200K system gates) although the board will accept the pin compatibleXC3S400-FT256 (400K system gates) or XC3S1000-FT256 (1M system gates) devices. The FPGA has I/O connections to: The AT91 microcontroller A local SRAM Expansion connectors Some local I/O (shared) The connections to the microprocessor also allow the FPGA to drive some of the on-board I/O. Except where unavoidable, the FPGA pad ring is supplied at 3.3V and I/O signals are normally expected to be `plain vanilla' I/O bits. Processor interface The FPGA is connected to the 16 dedicated data bus lines, 7 bus address lines (including A0 and A1), a two decoded chip select (with options on another two) and read and write strobes. The details and timing can be programmed on board the AT91. Although not intended for `typical' use, the bus wait signal can be employed; this signal would typically be used as an interrupt signal though. FIQ is available, as is a second/alternative interrupt if a port B pin is sacrificed. This allows the FPGA to implement peripherals driven directly from the ARM bus. The data bus can be widened to 32 bits by sacrificing some of the other facilities, most notably the on-board I/O such as the LCD. If the data bus is left as 16 (or 8) bit width, the 16 upper data lines can be used for general communication between the FPGA and the microcontroller in software (as PIO lines). These signals also have alternative functions as an I/O bus and to convey clocks, etc. RAM interface Two external 256Kx16 SRAM devices are hosted by the FPGA, allowing it to act as a stand-alone computer. These require: 32 data signals 18 address signals 2 nCS signals (one per RAM) with external pull ups 4 byte strobes 2 controls {nOE, nWE} shared between RAM chips Expansion connectors 80 I/O signals are made available via 5 connectors. These are all inputs with ???K passive pull-ups following reset. One connector (16 lines) are shared with half the on-board data bus to the local RAM; if these are required it may be that only half the RAM (16 bits wide) is available. Two signals are also used for on-board button inputs; the biasing of these may be different from other signals; series resistors make it safe to drive them from active outputs. Note, however, that these signals are also connected to the AT91 {PC4, PC5}; these will normally be inputs, but there is an option for the AT91 to drive either or both of these as extra chip select lines {NCS4, NCS5} if required and this will disqualify this pair of I/O lines {FPGA_IO_4_E8, FPGA_IO_4_O8} from other uses and the buttons should not be pressed in this case! Local I/O The on-board LEDs and LCD bus is shared with the processor (port C). The FPGA can drive these so care must be taken to ensure only one output is active at a given time. One suggestion is to use another PC bit as an FPGA output enable, so everything can be controlled by the processor. FPGA configuration The FPGA may be configured in two ways. The primary means is in the slave parallel "SelectMAP" mode and the mode pins (M2-0) are tied to this configuration. Remote JTAG loading is also possible in this configuration [**subject to proof on particular device**] which does not require the processor's intervention. Normal configuration is under the microcontroller's control and is done entirely via bits on PIO_C. PC0 PROG_B uC out Dedicated Initialise the FPGA for configuration PC1 CCLK uC out Dedicated Configuration strobe PC16 CS_B uC out Dual Fn. Low to select FPGA (hardly useful) PC17 RDWR_B uC out Dual Fn. Low to write FPGA Can be used for readback PC18 INIT_B uC in Dual Fn. Open drain `ready to load' (hardly useful) PC19 BUSY uC in Dual Fn. `Not listening' PC23-30 D7-0 data Dual Fn. Data for config. (or readback) PC23 is LSB If specified in the bit file, this interface can be retained for device readback. More usually the dual function pins will become general I/O and can be used for microcontroller communications or be floated so the FPGA can drive the on-board I/O. Pin Fn. Bank Name Function A1 GND GND A2 TDI * S_TDI A3 IO 0 RAM_D2 A4 IO 0 RAM_D5 A5 IO 0 RAM_D0 A6 VCCaux 2V5 A7 IO 0 RAM_D1 A8 IO/GCLK6 0 RAM_D19/FPGA_IO_5_ A9 IO 1 RAM_D20/FPGA_IO_5_ A10 IO 1 RAM_NUB1 A11 VCCaux 2V5 A12 IO 1 RAM_D21/FPGA_IO_5_ A13 IO 1 RAM_D26/FPGA_IO_5_ A14 IO 1 RAM_D24/FPGA_IO_5_ A15 TDO * S_TDO A16 GND GND B1 IO 7 FPGA_IO_1_O1 B2 GND GND B3 PROG_B * PC0 B4 IO 0 RAM_D4 B5 IO 0 RAM_D7 B6 IO 0 RAM_D11 B7 IO 0 RAM_D15 B8 IO/GCLK7 0 RAM_D18/FPGA_IO_5_ B9 GND GND B10 IO 1 RAM_NLB1 B11 IO 1 RAM_NCS0 Pull up B12 IO 1 RAM_D28/FPGA_IO_5_ B13 IO 1 RAM_D27/FPGA_IO_5_ B14 IO 1 RAM_D25/FPGA_IO_5_ B15 GND GND B16 IO 2 RAM_A1 C1 IO 7 FPGA_IO_1_E1 C2 IO 7 FPGA_IO_1_E2 C3 IO 7 FPGA_IO_1_O2 C4 HSWAP_EN * internal pull ??? C5 IO 0 RAM_D6 C6 IO 0 RAM_D10 C7 IO 0 RAM_D14 C8 IO 0 RAM_D17/FPGA_IO_5_ C9 IO/GCLK5 1 PB31 (PCK2) C10 IO 1 RAM_D22/FPGA_IO_5_ C11 IO 1 RAM_NUB0 C12 IO 1 RAM_D29/FPGA_IO_5_ C13 TMS * S_TMS C14 TCK * S_TCK C15 IO 2 RAM_A3 C16 IO 2 RAM_A2 D1 IO 7 FPGA_IO_1_E3 D2 IO 7 FPGA_IO_1_O3 D3 IO 7 FPGA_IO_1_O4 D4 VCCint 1V2 D5 IO 0 RAM_D3 D6 IO 0 RAM_D9 D7 IO 0 RAM_D13 D8 IO 0 RAM_D16/FPGA_IO_5_ D9 IO/GCLK4 1 PC10 (SCK0) D10 IO 1 RAM_NLB0 D11 IO 1 RAM_D30/FPGA_IO_5_ D12 IO 1 RAM_D23/FPGA_IO_5_ D13 VCCint 1V2 D14 IO 2 RAM_A4 D15 IO 2 RAM_A5 D16 IO 2 RAM_A6 E1 IO 7 FPGA_IO_1_E5 E2 IO 7 FPGA_IO_1_O5 E3 IO 7 FPGA_IO_1_E4 E4 IO 7 FPGA_IO_1_O6 E5 VCCint 1V2 E6 IO 0 RAM_D8 E7 IO 0 RAM_D12 E8 VCCO 0 3V3 E9 VCCO 1 3V3 E10 IO 1 RAM_NCS1 Pull up E11 IO 1 RAM_D31/FPGA_IO_5_ E12 VCCint 1V2 E13 IO 2 RAM_A7 E14 IO 2 RAM_A8 E15 IO 2 RAM_A9 E16 IO 2 RAM_A10 F1 VCCaux 2V5 F2 IO 7 FPGA_IO_1_E7 F3 IO 7 FPGA_IO_1_O7 F4 IO 7 FPGA_IO_1_E6 F5 IO 7 FPGA_IO_1_O8 F6 GND GND F7 VCCO 0 3V3 F8 VCCO 0 3V3 F9 VCCO 1 3V3 F10 VCCO 1 3V3 F11 GND GND F12 IO 2 RAM_A11 F13 IO 2 RAM_A12 F14 IO 2 RAM_A13 F15 IO 2 RAM_A14 F16 VCCaux 2V5 G1 IO 7 FPGA_IO_4_O3 G2 IO 7 FPGA_IO_4_E4 G3 IO 7 FPGA_IO_4_E1 G4 IO 7 FPGA_IO_4_O1 G5 IO 7 FPGA_IO_1_E8 G6 VCCO 7 3V3 G7 GND GND G8 GND GND G9 GND GND G10 GND GND G11 VCCO 2 3V3 G12 IO 2 RAM_A15 G13 IO 2 RAM_A16 G14 IO 2 RAM_A17 G15 IO 2 RAM_NWE G16 IO 2 RAM_A0 H1 IO 7 FPGA_IO_4_E3 H2 GND GND H3 IO 7 FPGA_IO_4_E2 H4 IO 7 FPGA_IO_4_O2 H5 VCCO 7 3V3 H6 VCCO 7 3V3 H7 GND GND H8 GND GND H9 GND GND H10 GND GND H11 VCCO 2 3V3 H12 VCCO 2 3V3 H13 IO 2 RAM_NOE H14 IO 2 PB30 (IRQ1) H15 IO 2 PC4/NCS4/FPGA_IO_4_E8/Button_A (ST3) H16 IO 2 PC5/NCS5/FPGA_IO_4_O8/Button_B (ST2) J1 IO 6 FPGA_IO_4_O7 J2 IO 6 FPGA_IO_4_E7 J3 IO 6 FPGA_IO_4_O6 J4 IO 6 FPGA_IO_4_E6 J5 VCCO 6 3V3 J6 VCCO 6 3V3 J7 GND GND J8 GND GND J9 GND GND J10 GND GND J11 VCCO 3 3V3 J12 VCCO 3 3V3 J13 IO 3 A4 J14 IO 3 A3 J15 GND GND J16 IO 3 A5 K1 IO 6 FPGA_IO_4_O4 K2 IO 6 FPGA_IO_4_O5 K3 IO 6 FPGA_IO_4_E5 K4 IO 6 FPGA_IO_2_O8 K5 IO 6 FPGA_IO_2_E8 K6 VCCO 6 3V3 K7 GND GND K8 GND GND K9 GND GND K10 GND GND K11 VCCO 3 3V3 K12 IO 3 FPGA_IO_3_E8 K13 IO 3 A2 K14 IO 3 PC11/FIQ/Button_C K15 IO 3 PC3/LCD_E K16 IO 3 A6 L1 VCCaux 2V5 L2 IO 6 FPGA_IO_2_O7 L3 IO 6 FPGA_IO_2_E7 L4 IO 6 FPGA_IO_2_O6 L5 IO 6 FPGA_IO_2_E6 L6 GND GND L7 VCCO 5 3V3 L8 VCCO 5 3V3 L9 VCCO 4 3V3 L10 VCCO 4 3V3 L11 GND GND L12 IO 3 FPGA_IO_3_O8 L13 IO 3 FPGA_IO_3_E6 L14 IO 3 FPGA_IO_3_O7 L15 IO 3 FPGA_IO_3_E7 L16 VCCaux 2V5 M1 IO 6 FPGA_IO_2_O5 M2 IO 6 FPGA_IO_2_E5 M3 IO 6 FPGA_IO_2_O4 M4 IO 6 FPGA_IO_2_E4 M5 VCCint 1V2 M6 IO/D7 5 PC23 M7 IO 5 D15 M8 VCCO 5 3V3 M9 VCCO 4 3V3 M10 IO 4 D6 M11 IO/D0 4 PC30 M12 VCCint 1V2 M13 IO 3 FPGA_IO_3_O6 M14 IO 3 FPGA_IO_3_E4 M15 IO 3 FPGA_IO_3_O5 M16 IO 3 FPGA_IO_3_E5 N1 IO 6 FPGA_IO_2_O3 N2 IO 6 FPGA_IO_2_E3 N3 IO 6 FPGA_IO_2_O2 N4 VCCint 1V2 N5 IO 5 D8 N6 IO 5 PC24 ------ N7 IO 5 D14 N8 IO/GCLK2 5 PC20/TIOB0 N9 IO/INIT_B 4 PC18 N10 IO 4 D7 N11 IO/D1 4 PC29 N12 IO 4 NWR1 N13 VCCint 1V2 N14 IO 3 FPGA_IO_3_O4 N15 IO 3 FPGA_IO_3_O3 N16 IO 3 FPGA_IO_3_E3 P1 IO 6 FPGA_IO_2_01 P2 IO 6 FPGA_IO_2_E2 P3 M0 * P4 M2 * P5 IO 5 D11 P6 IO 5 D13 P7 IO 5 D9 P8 IO/GCLK3 5 PC21/TIOA1 P9 IO/BUSY 4 PC19 P10 IO/D2 4 PC28 P11 IO 4 D4 P12 IO 4 D2 P13 IO 4 NWR2/A1 P14 IO 3 FPGA_IO_3_O2 P15 IO 3 FPGA_IO_3_E2 P16 IO 3 FPGA_IO_3_E1 R1 IO 6 FPGA_IO_2_E1 R2 GND GND R3 IO/CS_B 5 PC16/LCD_RS R4 IO 5 NCS2 R5 IO 5 PC2/NWAIT/IRQ0 R6 IO 5 D12 R7 IO/D5 5 PC25 R8 GND GND R9 IO/GCLK1 4 PC31/PCK1 R10 IO/D3 4 PC27 R11 IO 4 D5 R12 IO 4 D3 R13 IO 4 NWR3 R14 DONE * N/C R15 GND GND R16 IO 3 FPGA_IO_3_O1 T1 GND GND T2 M1 * T3 IO/RDWR_B 5 PC17/LCD_RW T4 IO 5 NCS1 T5 IO 5 A0 T6 VCCaux 2V5 T7 IO/D4 5 PC26 T8 IO 5 D10 T9 IO/GCLK0 4 PC22/TIOB1 T10 IO 4 D1 T11 VCCaux 2V5 T12 IO 4 D0 T13 IO 4 NRD T14 IO 4 NWR0 T15 CCLK * PC1 T16 GND GND FPGA clocks The FPGA has eight inputs which may import clock signals. Six are wired to potential clock sources. GCLK0 TIOB1 CTC I/O GCLK1 PCK1 May be programmed on uC. Default ~24MHz GCLK2 TIOB0 CTC I/O GCLK3 TIOA1 CTC I/O GCLK4 SCK0 Serial clock from uC Default 1.8432MHz(???) (115K2 baud) GCLK5 PCK2/50MHz Link selectable from uC/osc. [PCK2 shared with PB31] GCLK6 ---- GCLK7 ---- The FPGA may adjust clock frequencies on board, multiplying and dividing by numbers in the range 1..32 Connections from AT91 to FPGA Name Function AT91 function FPGA function uC Dir. Notes D[15:0] Data bus Data bus Data bus Bi. AT91 is master A[6:0] Address bus Address bus Address bus Out AT91 is master NCS[2:1] Chip selects IO Out NWR[3:0] Write strobes IO Out NRD Read strobe IO Out PB[30] Spare IRQ IRQ1/IO IO (In) PB[31] Spare Clock PCK2/IO GCLK5/IO (Out) PC[0] PROG_B IO Reset Out Initialise FPGA PC[1] CCLK IO Strobe Out Programme FPGA *2 PC[2] wait/IRQ nWait/IRQ0/IO IO (In) PC[3] LCD_E IO IO Out 10K pull down PC[4] SW_2 IO IO (In) Use internal pull up PC[5] SW_1 IO IO (In) Use internal pull up PC[10] Serial clock SCK0/IO GCLK4/IO Out PC[11] SW_3/FIQ FIQ/IO IO In Use internal pull up PC[16] CS_B/LCD_RS IO IO (Out) FPGA config. PC[17] RDWR_B/LCD_RW IO IO (Out) FPGA config. PC[18] Init_B IO IO (In) FPGA config. *3 PC[19] Busy IO IO (In) FPGA config. PC[20] TIOB0/IO GCLK3/IO (Out) PC[21] TIOA1/IO GCLK2/IO (Out) PC[22] TIOB1/IO GCLK0/IO (Out) PC[23] SW_bus[0] IO IO (Bi) Startup switch PC[24] SW_bus[1] IO IO (Bi) Startup switch PC[25] SW_bus[2] IO IO (Bi) Startup switch PC[26] SW_bus[3] IO IO (Bi) Startup switch PC[27] SW_bus[4] IO IO (Bi) PC[28] SW_bus[5] IO IO (Bi) PC[29] SW_bus[6] IO IO (Bi) PC[30] SW_bus[7] IO IO (Bi) PC[31] Main Clock PCK1/IO GCLK1/IO (Out) PC[31:16] can also act as the high bits of a 32-bit data bus. SW_bus[7:0] connects to the LED data, LCD data and the FPGA programming ports. Board pinout Signal names Connector number PA[15:0] JT18 PA[31:16] JT13 PB[15:0] JT19 PB[31:16] JT6 FPGA_IO_1 JT7 FPGA_IO_2 JT14 FPGA_IO_3 JT2 FPGA_IO_4 JT12 FPGA_IO_5 JT3 Footnotes *1 For the switch to be read successfully the FPGA must not affect the levels accidentally. The pull-up/-down resistors in the Spartan 3 are unusually small (~few K) and thus must not be enabled. If the FPGA is unprogrammed, this is prevented by HSWAP_EN floating (high); when the FPGA is programmed this can change, especially if the particular pin is not used. To prevent this the correct option needs setting in the compilation tools. "The Bitstream Generator (Bitgen) option UnusedPin available in the Xilinx development software determines whether unused I/Os collectively have pull-up resistors, pull-down resistors, or no resistors in User mode." (i.e. "Pullnone" - NOT the default option.) *2 Positive edge triggered clock. Best left in low state to reduce reverse current onto 2V5 supply (Vccaux) from clamping diodes. *3 Uses internal pull-up in FPGA (and AT91). Not clear quite what, but both should be available ???.