COMP32211 Implementing System-on-Chip Designs syllabus 2019-2020
The ultimate goal of any hardware design is a physical implementation. This course covers the translation of algorithms into a realisable hardware design. The practical part of the course develops higher level models into Verilog HDL and thence to an FPGA. In the lectures the process of mapping designs to ASICs is studied with emphasis on practicalities such as trading chip area, delays, power, etc. to meet a specification. Emphasis is also given to areas which are used extensively in the practical work, particularly simulation, debugging and verification.
The module aims to give an overview of the processes involved in taking a concept onto a product chip. It also illustrates some of the choices available to an implementer. Finally, the practicals are intended to give some experience of the flow, the frustration and the satisfaction of making a working device.
The practical part of the course involves migrating the design of a moderately complex FSM into Verilog, integrating it with other parts of a system-on-chip, verifying that it operates correctly and demonstrating it working. The intention is to use a graphics drawing example design so that the final result can easily be seen on its own display.
The lectures are planned approximately as follows:
The scale of the problem and what VLSI 'looks like', inside.
Some revision plus some features you may not have met before.
Test harness construction and making things 'realistic'.
What to look for and how to find it.
The sort of tools used to get source code into silicon and how to get the best from them.
Simulating big designs and getting sufficiently accurate results in days, not months.
Clocking, clock distribution and the perils of crossing between clock domains.
What every VLSI engineer needs to know about CMOS
Overcoming the crippling effects of reality on a nice, clean design.
Proving the device will work and then checking if it does when the silicon arrives.
Silicon fabrication is still evolving rapidly. A look at some things which are going to make life (even) harder.
2 hours/week (1 hour timetabled, 1 hour independent work)
Feedback methodsFeedback is given orally in scheduled laboratories; lectures are intended to be active and discussion is encouraged.
Annotated listings and diagrams will be returned to students.
Feedback as to whether a constructed (video) system operates correctly should be apparent from simulations during the work's progression and will definitely visible in the final realisation.
- Assessment written exam (2 hours)
- Lectures (12 hours)
- Practical classes & workshops (12 hours)
- Analytical skills
- Problem solving
On successful completion of this unit, a student will be able to:
- exhibit improved ability in digital design skills using CAD tools, focused on Verilog HDL
- design, implement and verify an RTL FSM
- plan and carry out digital hardware verification to a credible standard
- interpret technical specifications of digital hardware interfaces and conform to the same
- exhibit a vocabulary of terminology enabling the discussion of the ASIC design flow, as used industrially, with professional engineers
COMP32211 does not have a specified reading list.
Course unit materials
Links to course unit teaching materials can be found on the School of Computer Science website for current students.