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COMP20212: Digital Design Techniques (2007-2008)

This is an archived syllabus from 2007-2008

Digital Design Techniques
Level: 2
Credit rating: 10
Pre-requisites: COMP10211 , (COMP10222 recommended)
Co-requisites: No Co-requisites
Duration: 11 weeks in second semester
Lectures: 22 in total, 2 per week
Examples classes: 4
Labs: 15 hours in total, 5 3-hour sessions, partly credited to COMP20910/COMP20920
Lecturers: Ernie Hill, Paul Nutter
Course lecturers: Ernie Hill

Paul Nutter

Additional staff: view all staff
Timetable
SemesterEventLocationDayTimeGroup
Sem 2 w19-25,29-32 Lecture LF17 Wed 11:00 - 12:00 -
Sem 2 w19-25,29-32 Lecture LF17 Fri 14:00 - 15:00 -
Sem 2 w19,21,23,25,30,32 Examples IT406 Thu 15:00 - 16:00 -
Sem 2 w20,22,24,29,31 Lab Eng Thu 13:00 - 16:00 -
Assessment Breakdown
Exam: 75%
Coursework: 10%
Lab: 15%

Aims

Modern computer systems are designed using CMOS logic. This course introduces the design options and implementation techniques available for the design of modern CMOS digital systems. This is achieved by emphasising the top down approach to the development of a digital design.

Learning Outcomes

At the end of the course students should be able to:

Know the importance of hierarchy in the design of complex digital systems (A).
Know the different levels of abstraction used to represent logic systems and be familiar with the data representation and method of simulation at each level (A).
Understand the requirements of full- and semi-custom CMOS logic design (A).
Design and layout full custom logic blocks (B).
Understand the requirements of PAL, PLA and FPGA logic architectures for logic synthesis (A).
Understand the important trade-offs between different implementation styles (A, B).
Design a FSM from an algorithmic description of a problem (B).
Design the data path for a RISC processor and synthesise the control logic (A,B,C).

Assessment of Learning outcomes

Learning outcomes 3, 4 and 7 are assessed by examination and in the laboratory. Learning outcomes 1, 2, 5 and 6 are assessed by examination. Learning outcome 8 is assessed by the laboratory.

Contribution to Programme Learning Outcomes

A3, B1, B2, C1, C6, D2, D4, D5

Syllabus

Introduction



Overview, aims and objectives of the course. Walk-through of the laboratory design exercise. Top down design, design complexity, managing complexity: levels of abstraction, algorithmic specification - using a RISC processor (STUMP) as an example (2)

Layout


Stick diagrams, geometric design rules, floorplan organisation (2).

CMOS circuit design


Basic gates, complex gates, PLA's, full adder example. Transmission gates multiplexers and Universal Logic Modules. Dynamic logic (3).

CMOS fabrication



Photolithography, stages of CMOS processing, yield, wafer testing, packaging (2).

Scaling


Effect of scaling parameters and interconnect delays (2).

Power, speed and space compromises


Transistor sizing and the inverter delay, RC delay model - rise and fall propagation delay (2) .

Circuit simulation


SPICE simulation and real propagation delays (1).

Digital implementation choices


Design choices - off-the-shelf range, semi-custom gate array, semi-custom standard cell, full-custom, comparison of design styles. Programmable vs. full- and semi-custom implementation (1).

Digital design with programmable logic devices


The PLA and PAL, Fusible link devices, ROM based implementation, FPGA and RAM routable gate arrays (3).

Data path and sequential system design


Data path design. Control synthesis - Revision of FSM's and bubble graphs. Sequential design using the ASM chart. Example ASM charts, Mealy and Moore machines, link path extraction, looping. RISC processor example (STUMP). State assignment, minimum state locus, one-hot state encoding. State tables and forming logic. Map entered variables, linked state machines (4).

Examples classes


Examples Class on CMOS layout design.

Examples Class on CMOS circuit design.

2 examples classes on programmable logic and sequential design.

The examples classes are allocated to assessed coursework. Students are expected to complete (in their own time) small design exercises, similar to, but longer than, problems that are set in the exam.

Reading List

Core Text
Title: Digital Systems Design Using VHDL
Author: Charles H. Roth
ISBN: 0495244708
Publisher: PWS
Edition: Edition Student Manual/Study Guide
Year: 1998


Core Text
Title: CMOS VLSI design: a circuits and systems perspective (3rd edition)
Author: Weste, Neil H.E. and David Harris
ISBN: 0321269772
Publisher: Pearson Education Limited
Edition: 3rd
Year: 1993