COMP30002: High Performance Microprocessors (2007-2008)
It is perfectly possible to write programs and get them to work without much detailed understanding of either (1) how a compiler turns the source code into machine code, or (2) how a computer executes the machine code. However, to make the resulting program run quickly (perform well), such an understanding is essential. This course provides the necessary material in the context of modern microprocessor designs. The course is based on the renowned book "Computer Architecture - A Quantitative Approach" by John Hennessy and David Patterson.
Modern computer systems are almost exclusively constructed from single-chip microprocessors, increasingly now with multiple core Central Processing Units. As fabrication density and integration levels have increased, microprocessor manufacturers have adopted many of the architectural ideas first devised for the previous generations of high-performance computers. The aim of this course is to provide a thorough understanding of the machine architectural and associated compilation techniques used in current microprocessors and to examine their performance characteristics. Advanced techniques, which may find their way into the next generation of products, are also examined and analysed.
A student completing this course should:
Have an understanding of trends in the development of microprocessor systems. (A)
Have knowledge of the techniques used to benchmark modern computer systems. (A)
Understand the techniques used in microprocessor micro-architecture and be able to produce designs of the elements of a processor core. (A and B)
Understand the structure of memory hierarchy in modern microprocessor systems and be able to produce designs of such systems. (A and B)
Have an understanding of future trends in microprocessor technology and how these are likely to affect the development of computer systems. (A)
Assessment of Learning outcomesAll learning outcomes are assessed by examination.
Contribution to Programme Learning OutcomesA3, B1, B2, B3
Trends in technology, cost and computer usage. Measuring and reporting performance; benchmarking and benchmarks.
Instruction Level Parallelism 
Pipelining revisited. Data hazards, dynamic scheduling. Branch prediction: static, dynamic. Zero-cycle branches. Multiple Issue implementations. Compiling for superscalar implementations. Hardware support for instruction level parallelism.
Memory Hierarchy 
Cache memory: block organization; cache line placement, replacement and write policies. Write buffering. Classifying misses: compulsory/capacity/conflict misses. Reducing misses: line size, associativity, victim cache, prefetching, compiler optimizations. Reducing miss penalty: reordering memory cycles, subblock placement, early restart, lockup-free operation, multilevel caches. Reducing hit time. Main memory and its performance.
Case Studies 
Intel Pentium Pro - Superscalar RISC implementation of a CISC instruction set. Dec Alpha - a 'clean-sheet' superscalar RISC architecture. PowerPC - a pragmatic combination of features.
Multicore Chips 
The trend to multicore; anticipated `roadmap'. Specifics of Intel Core Duo and Quad chips.
The Future 
Future technology limitations. The requirement for Mobile code; JAVA implementation techniques, JIT compilation. Dynamic optimizations. Virtualization.
The recommended text (see below) is for reference only; it is the most famous book on computer architecture. There is no need to buy a copy unless you intend to make a career out of microprocessor design. The overnight loan library has three copies of the third edition at the moment; a copy of the fourth edition is on order (as of January 2008).
Core TextTitle: Computer architecture: a quantitative approach (5th edition)
Author: Hennessy, John L. and David A. Patterson
Publisher: Morgan Kaufmann
The latest edition of "the computer architect's bible". A comprehensive reference work covering all aspects of modern microprocessor architecture. Not necessary to own unless you are a committed computer architect.