Skip to navigation | Skip to main content | Skip to footer
Menu
Menu

COMP10211: The Underlying Machine (2008-2009)

This is an archived syllabus from 2008-2009

The Underlying Machine
Level: 1
Credit rating: 10
Pre-requisites: No Pre-requisites
Co-requisites: Preferred for students to take COMP10031
Duration: 11 weeks in first semester
Lectures: 22 in total, 2 per week
Examples classes: none
Labs: 20 hours in total, 10 2-hour sessions
Lecturers: Jim Garside, Ernie Hill
Course lecturers: Doug Edwards

Jim Garside

Ernie Hill

Additional staff: view all staff
Timetable
SemesterEventLocationDayTimeGroup
Sem 1 w1-5,7-12 Lecture 1.1 Wed 11:00 - 12:00 -
Sem 1 w1-5,7-12 Lecture 1.1 Tue 16:00 - 17:00 -
Sem 1 w2-5,7-12 Lab Toot 1 Wed 09:00 - 11:00 X
Sem 1 w2-5,7-12 Lab Toot 1 Tue 10:00 - 12:00 Y
Sem 1 w2-5,7-12 Lab Toot 1 Thu 13:00 - 15:00 Z
Sem 1 w2-5,7-12 Lab Toot 1 Thu 15:00 - 17:00 W
Assessment Breakdown
Exam: 50%
Coursework: 0%
Lab: 50%
Degrees for which this unit is core
  • Artificial Intelligence BSc (Hons)

Aims

This course introduces digital logic and its application in computer organisation and design.

The major emphasis is on practical design work and, in the laboratory, state-of-the-art computer-aided design tools are used to support the design of digital hardware systems. Students' designs are simulated and then implemented using electrically reconfigurable gate arrays.

The lectures initially support the laboratories but progress to a wider overview of the design and interaction of computer hardware systems. Ultimately a complete - if simple - computer is described as constructed from simple gates.

Learning Outcomes

A student completing this course unit should:

Have an understanding of the hierarchical design of complex digital systems including processors and memory. (A3,B3)
Have a knowledge of gate-level logic design. (A2)
Be able to design combinatorial circuits and small FSMs. (B1,B2)
Be able to use CAD support tools including design entry and simulation. (C6)

Assessment of Learning outcomes

Learning outcome (1) is not assessed directly in this course.

Learning outcomes (2), (3) and (4) are assessed in the laboratory.

Contribution to Programme Learning Outcomes

A2, A3, B1, B2, B3, C6

Syllabus

Basic logic functions (5)
Combinatorial logic
Sequential logic

Register Transfer Level (3)

The `three box' computer model (1)

Processors (4)
Datapath design
Control
Optimisation

Memory (4)
Types of memory
Addressing and interfacing

Input/output (3)
Parallel I/O
Serial I/O

Alternative computational models (2)

Reading List

Title: Computer systems architecture: a networking approach
Author: Williams, Rob
ISBN: 0201648598
Publisher: Addison-Wesley
Edition:
Year: 2001
An alternative coverage of hardware topics.


Title: Principles of computer hardware (4th edition)
Author: Clements, Alan
ISBN: 9780199273133
Publisher: Oxford University Press
Edition: 4th
Year: 2006
A good coverage of basic computer hardware reaching beyond the scope of this course. Also covers the ARM processor.