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COMP20241: VLSI System Design (2009-2010)

This is an archived syllabus from 2009-2010

VLSI System Design
Level: 2
Credit rating: 10
Pre-requisites: COMP10211
Co-requisites: No Co-requisites
Duration: 11 weeks in first semester
Lectures: 17
Examples classes: None
Labs: 16 hours in total
Lecturers: Linda Brackenbury
Course lecturer: Linda Brackenbury

Additional staff: view all staff
Timetable
SemesterEventLocationDayTimeGroup
Sem 1 w1-5,7-12 Lecture LF15 Fri 11:00 - 12:00 F
Sem 1 w1-2 Lecture LF15 Tue 10:00 - 12:00 F
Sem 1 w3-5,7-12 Lab Toot 1 Tue 10:00 - 12:00 F
Sem 1 w3-5,7-12 Lab Toot 1 Tue 15:00 - 17:00 G
Sem 1 w12 Lecture 1.3 Tue 10:00 - 12:00 F
Assessment Breakdown
Exam: 50%
Coursework: 0%
Lab: 50%
Degrees for which this unit is optional
  • Artificial Intelligence BSc (Hons)

Aims

The course gives an understanding of how integrated circuit technology is used today to implement complex electronic systems as silicon chips. VLSI circuits play an increasingly important role in computer systems; it is therefore of benefit to a wide range of computer scientists to know how this technology can be exploited and to be aware of the many factors involved in the design of a VLSI chip.

Learning Outcomes

A student completing this course unit should:

Have a knowledge and understanding of the process of designing VLSI chips (A and C).
Have a knowledge and understanding of industry-standard hardware description languages (A, B and C).
Have an understanding of the different design stages and representations of a VLSI circuit (A, B and C).
Have an understanding of the major architectural and performance factors to be considered in the global design of a large integrated circuit (A).
Have an understanding and appreciation of the problems arising out of the rapid change of technology and increase in design complexity (A).
Be able to design a 16-bit RISC processor at the upper levels of the design process, and have experience of the tools to test and debug the design (A, B, C and D).

Assessment of Learning outcomes

Learning outcomes (1), (2) (3) and (6) are assessed by examination and in the laboratory. Learning outcomes (4) and (5) are assessed by examination.

Contribution to Programme Learning Outcomes

A3, B1, B2, B3, C1, C2, C5, C6, D4, D5

Syllabus

Introduction (2)


Scales of integration, CMOS versus other technologies, VLSI trends, overview of top down design hierarchy, VLSI design route.

System Specification of the STUMP (2)


RISC versus CISC, load/store architecture, non-pipelined behaviour, instruction set.

Top-Level Behavioural Description (1)


Flow diagram.

Architectural Design of STUMP (1)


Block partitioning, datapath occupancy.

Register Transfer Level Design (1)


Formation of STUMP datapath.

Verilog Hardware Description Language (4)


Principles, structure, features and syntax, scheduling, test bench.

Testability (2)


Partitioning, signature analysis, scanpath, boundary scan, built-in self test.

Timing and Clocking (2)


Asynchronous versus synchronous, single and two-phase clocking schemes, clock generation, buffering, and distribution.

Logic Design (2)


Datapath: synthesis, bit slice approach, ad hoc logic, structured logic.

Control: ad hoc, finite state machines, use of PLAs.