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COMP35111: Chip Multiprocessors (2010-2011)

This is an archived syllabus from 2010-2011

Chip Multiprocessors
Level: 3
Credit rating: 10
Pre-requisites: COMP25212 (was 20092) System Architecture
Co-requisites: No Co-requisites
Lecturers: Chris Kirkham, Ian Watson
Course lecturers: Chris Kirkham

Ian Watson

Additional staff: view all staff
Timetable
SemesterEventLocationDayTimeGroup
Sem 1 Lecture 1.5 Mon 10:00 - 11:00 -
Sem 1 Lecture 1.4 Wed 12:00 - 13:00 -
Assessment Breakdown
Exam: 75%
Coursework: 25%
Lab: 0%

Themes to which this unit belongs
  • Computer Architecture

Introduction

Due to technological limitations, it is proving increasingly difficult to maintain a continual increase in the performance of individual processors. Therefore, the current trend is to integrate multiple processors on to a single chip and exploit the resulting parallel resources to achieve higher computing power. However, this may require significantly different approaches to both hardware and software particularly for general purpose applications. This course will explore these issues in detail.

Syllabus

Introduction

Trends in technology, limitations and consequences. The move to multi-core
Parallelism in programs, ILP, Thread Level, Data Parallelism.

Parallel Architectures

SIMD, MIMD, Shared Memory, Distributed Memory, strengths & weaknesses.

Parallel Programming

Multithreaded programming, Data parallel programming, Explicit vs Implicit parallelism, automatic parallelisation. The Case for Shared Memory. When to share?

Shared Memory Multiprocessors

Basic structures, the cache coherence problem. The MESI protocol. Limitations. Directory based coherence.

Programming with Locks & Barriers

The need for synchronisation. Problems with explicit synchronisation

Other Parallel Programming Approaches

MPI & OpenMP

Speculation

The easy route to automatic parallelisation?

Transactional Memory

Principles. Hardware & Software approaches

Memory Issues

Memory system design. Memory consistency

Other Architectures & Programming Approaches

GPGPUs, CUDA

Data Driven Parallelism

Dataflow principles & Functional Programing