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COMP32212: Implementing System-on-Chip Designs (2011-2012)

This is an archived syllabus from 2011-2012

Implementing System-on-Chip Designs
Level: 3
Credit rating: 10
Pre-requisites: COMP22111, COMP32111
Co-requisites: No Co-requisites
Duration: 11 weeks in semester 2
Lectures: 11
Labs: 2 hours/week (1 hour timetabled, 1 hour independent work)
Lecturers: Jim Garside, Ernie Hill
Course lecturers: Jim Garside

Ernie Hill

Additional staff: view all staff
Timetable
SemesterEventLocationDayTimeGroup
Sem 2 Lecture G33 Tue 15:00 - 16:00 -
Sem 2 Lab Toot 0 Tue 16:00 - 17:00 -
Assessment Breakdown
Exam: 50%
Coursework: 0%
Lab: 50%

Themes to which this unit belongs
  • System-on-Chip

Introduction

The ultimate goal of any hardware design is a physical implementation. This course complements COMP32111 by examining the process of realising a design in hardware. The practical part of the course develops higher level models into Verilog HDL and thence to an FPGA. In the lectures the process of mapping designs to ASICs is studied with emphasis on practicalities such as trading chip area, delays, power, etc. to meet a specification. Emphasis is also given to areas which are used extensively in the practical work, particularly simulation, debugging and verification.

Aims

The module aims to give an overview of the processes involved in taking a concept onto a product chip. It also illustrates some of the choices available to an implementer. Finally, the practicals are intended to give some experience of the flow, the frustration and the satisfaction of making a working device.

Programme outcomeUnit learning outcomesAssessment
A2 B1 B2 B3 C1 C5 C6 C9 D4Have implemented a substantial hardware unit.
  • Lab assessment
  • Examination
A3 B1 B2 C1 C6 D5Have integrated that unit into a larger hardware design.
  • Examination
  • Lab assessment
C5 C6Have developed greater understanding of HDLs.
  • Examination
B2 C4 D4Be a more confident digital hardware designer.
  • Examination

Syllabus

The practical part of the course involves migrating the design of a moderately complex FSM into Verilog, integrating it with other parts of a system-on-chip, verifying that it operates correctly and demonstrating it working. The intention is to use a graphics drawing example design so that the final result can easily be seen on its own display.

The lectures are planned approximately as follows:

Introduction
The scale of the problem and what VLSI 'looks like', inside.

Verilog
Some revision plus some features you may not have met before.

Functional Simulation
Test harness construction and making things 'realistic'.

Debugging
What to look for and how to find it.

Tool flows
The sort of tools used to get source code into silicon and how to get the best from them.

Timing Simulation
Simulating big designs and getting sufficiently accurate results in days, not months.

Timing
Clocking, clock distribution and the perils of crossing between clock domains.

Technology
What every VLSI engineer needs to know about CMOS

Layout
Overcoming the crippling effects of reality on a nice, clean design.

Testing
Proving the device will work and then checking if it does when the silicon arrives.

Future
Silicon fabrication is still evolving rapidly. A look at some things which are going to make life (even) harder.