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COMP12111: Fundamentals of Computer Engineering (2012-2013)

This is an archived syllabus from 2012-2013

Fundamentals of Computer Engineering
Level: 1
Credit rating: 10
Pre-requisites: No Pre-requisites
Co-requisites: Preferred for students to take COMP15111
Duration: 11 weeks in first semester
Lectures: 22 in total, 2 per week
Examples classes: none
Labs: 20 hours in total, 10 2-hour sessions
Course Leader: Paul Nutter
Additional Lecturers: Ernie Hill
Course leader: Paul Nutter

Additional staff: view all staff
Timetable
SemesterEventLocationDayTimeGroup
Sem 1 Lecture 1.1 Mon 12:00 - 13:00 -
Sem 1 Lecture 1.1 Fri 12:00 - 13:00 -
Sem 1 w2+ Lab Toot 1 Wed 09:00 - 11:00 X
Sem 1 w2+ Lab Toot 1 Thu 13:00 - 15:00 Z
Sem 1 w2+ Lab Toot 1 Tue 13:00 - 15:00 Y
Sem 1 w2+ Lab Toot 1 Thu 15:00 - 17:00 W
Assessment Breakdown
Exam: 50%
Coursework: 0%
Lab: 50%

Introduction

This course introduces digital logic and its application in computer organisation and design.

The major emphasis is on practical design work and, in the laboratory, state-of-the-art computer-aided design tools are used to support the design of digital hardware systems. Students' designs are simulated and then implemented using electrically reconfigurable gate arrays.

The lectures initially support the laboratories but progress to a wider overview of the design and interaction of computer hardware systems. Ultimately a complete - if simple - computer is described as constructed from simple gates.

Aims

The main aim of this course is to give students a basic understanding of the hardware which underpins computing systems.

Further aims include:

Introduction to basic logic and logic gates
Partitioning of simple systems into combinatorial and sequential blocks
To introduce basic CAD tools to aid in the design of a basic computer system
To provide an overview of hardware description languages with particular emphasis on Verilog
Introducing logic level implementation of a simple processor
Discussion of how computer systems interact with memory and I/O devices

Programme outcomeUnit learning outcomesAssessment
A3 B3Have an understanding of the hierarchical design of complex digital systems including processors and memory.
A2Have a knowledge of gate-level logic design.
  • Lab assessment
B1 B2Be able to design combinatorial circuits and simple FSMs.
  • Lab assessment
C6Be able to use CAD support tools including design entry via schematic and Verilog, as well as simulation.
  • Lab assessment

Syllabus

Basic logic functions (4)
Combinatorial logic
Sequential logic

Register Transfer Level (3)

Introduction to CAD and Verilog (3)
The use of computer aided design to manage complex designs
Verilog as a hardware description language

The 'three box' computer model - CPU, Memory and I/O (1)

Processor Design (4)
Datapath design
Control
Optimisation

Memory (3)
Types of memory
Addressing and interfacing

Input/output (4)
Parallel I/O
Serial I/O
Interrupts and DMA

Reading List

Title: Digital design with RTL design, Verilog and VHDL (2nd edition)
Author: Vahid, Frank
ISBN: 9780470531082
Publisher: Wiley
Edition: 2nd
Year: 2010


Title: Principles of computer hardware (4th edition)
Author: Clements, Alan
ISBN: 9780199273133
Publisher: Oxford University Press
Edition: 4th
Year: 2006
A good coverage of basic computer hardware reaching beyond the scope of this course. Also covers the ARM processor.


Supplementary Text
Title: Computer systems architecture: a networking approach
Author: Williams, Rob
ISBN: 0201648598
Publisher: Addison-Wesley
Edition:
Year: 2001


Supplementary Text
Title: Digital design (4th edition)
Author: Morris Mano, M. and Michael D. Ciletti
ISBN: 9780132340434
Publisher: Pearson
Edition: 4th
Year: 2007


Supplementary Text
Title: Fundamentals of logic design (7th edition)
Author: Roth, Charles H. and Larry L. Kinney
ISBN: 9781133628484
Publisher: Cengage Learning
Edition: 7th
Year: 2014