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COMP22111: Processor Microarchitecture (2012-2013)

This is an archived syllabus from 2012-2013

Processor Microarchitecture
Level: 2
Credit rating: 10
Pre-requisites: COMP12111
Co-requisites: No Co-requisites
Duration: 11 weeks in first semester
Lectures: 15
Examples classes: None
Labs: 18 hours in total
Course Leader: Paul Nutter
Additional Lecturers: Jim Garside
Course leader: Paul Nutter

Additional staff: view all staff
Timetable
SemesterEventLocationDayTimeGroup
Sem 1 Lecture 1.5 Thu 14:00 - 15:00 -
Sem 1 w1-2,12 Lecture LF15 Tue 10:00 - 12:00 -
Sem 1 w3+ Lab Toot 0 Tue 10:00 - 12:00 -
Sem 1 w3+ Lab Toot 1 Tue 10:00 - 12:00 -
Sem 1 w11 Lecture LF15 Mon 15:00 - 16:00 -
Assessment Breakdown
Exam: 55%
Coursework: 45%
Lab: 0%

Themes to which this unit belongs
  • System-on-Chip

Introduction

Formerly called "VLSI System Design" - the module title has been updated to reflect the syllabus better.

This module aims to develop the two key aspects of COMP12111, namely hardware design and microprocessors. COMP12111 gave an overview of the hardware development process; COMP22111 builds on these skills to introduce and exercise industrially relevant hardware skills with a design flow from concept to implementation. It used microprocessors as design examples to illustrate and reinforce how machine code, output from a compiler, is interpreted and executed by a computer.

Much of the emphasis is on practical work and the laboratories take a microprocessor design through from an instruction set specification to a physical FPGA implementation. The lectures complement this and extend the scope towards the processes necessary to turn this into custom silicon.

Aims

The module aims to give a view of the role of a digital hardware designer, taking an idea and implementing it as a silicon chip. A processor is a representative example of logic used in today's chips, also giving further insight into how computers actually work.

Having completed the module you should have developed the confidence to be able to take a concept and realise it in hardware. You should also appreciate the test and verification processes involved so that your chips work efficiently and reliably ... first time, every time!

Programme outcomeUnit learning outcomesAssessment
A3Have a knowledge and understanding of the process of designing VLSI chips.
  • Lab assessment
  • Examination
A3Have an understanding of the different design stages and representations of a VLSI circuit.
  • Lab assessment
  • Examination
A3Have an understanding of the major architectural and performance factors to be considered in the global design of a large integrated circuit.
  • Examination
A3Have an understanding and appreciation of the problems arising out of the rapid change of technology and increase in design complexity.
  • Examination
A3 B1 B2 B3 C1 C2 C5 C6 D4 D5Be able to design a 16-bit RISC processor at the upper levels of the design process, and have experience of the tools to test and debug the design.
  • Lab assessment
  • Examination
A3 C5 C6Have a knowledge and understanding of industry-standard hardware description languages.
  • Examination
  • Lab assessment

Syllabus

Introduction (2)

Scales of integration, CMOS versus other technologies, VLSI trends, overview of top down design hierarchy, VLSI design route.

Verilog Hardware Description Language (4)

Principles, structure, features and syntax, scheduling & parallelism, hierarchical structures; test benches.

The STUMP - an example RISC(2)

RISC versus CISC, load/store architecture, non-pipelined behaviour, instruction set.

An example CISC (1)

A look at a CISC instruction set as a point of comparison.

Architectural Design of STUMP (1)

Block partitioning, datapath occupancy.

Register Transfer Level Design (1)

Formation of a STUMP datapath.

Finite State Machines (1)

The application of FSMs and their implementation in Verilog.

Design Flows (1)

CAD tools from concept to (working) chip.

Verification and Testing (1)

Modelling and testing designs at different levels of abstraction, yields and testing chips, test coverage.

Timing and Clocking (1)

Clock generation, buffering, and distribution; crossing clock domains.

Technology (1)

VLSI structures, standard cells, macrocells, ASICs and FPGAs.