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COMP32111: System-on-chip Modelling with SystemC (2012-2013)

This is an archived syllabus from 2012-2013

System-on-chip Modelling with SystemC
Level: 3
Credit rating: 10
Pre-requisites: COMP22111
Co-requisites: COMP32212
Duration: 11 weeks in semester 1
Lectures: 10
Labs: 2 hours/week (1 hour timetabled, 1 hour independent work)
Course Leader: Steve Furber
Additional Lecturers: Alasdair Rawsthorne
Course leader: Steve Furber

Additional staff: view all staff
Timetable
SemesterEventLocationDayTimeGroup
Sem 1 Lecture Alan Turing G.108 Mon 11:00 - 12:00 -
Sem 1 w1 Lecture LF17 Mon 12:00 - 13:00 -
Sem 1 w2+ Lab Toot 1 Mon 12:00 - 13:00 -
Assessment Breakdown
Exam: 50%
Coursework: 0%
Lab: 50%

Themes to which this unit belongs
  • System-on-Chip

Introduction

Microchips have become an inescapable feature of life since they are used in almost every piece of electronic equipment. The design of a modern SoC is a complex task involving a range of skills and a deep understanding of a hierarchy of perspectives on design, from processor architecture down to signal integrity. This course is one component of a 3-course theme that aims to show how correctly working chips can be obtained by presenting and demonstrating the techniques and stages used in the design and implementation of chips. Such an understanding of System-on-Chip is essential to anyone who wishes to become involved in any aspect of chip design. Since leading-edge industry-standard software tools and languages are taught and practised, the skills gained with this theme are directly transferable into companies and post-graduate research in this area. In addition, the theme will be of use to anyone who has an interest in hardware design and of interest to a wide range of computer scientists since it is of benefit to know how this technology can be exploited and to be aware of the many factors involved in the design of a chip.

Aims

This course introduces high-level design methodologies for System-on-Chip (SoC) where there are many computational blocks communicating with one another via channels. It will provide insights into these processes with the overall aim of introducing the main tools and techniques employed at the higher levels of complex SoC design and to provide an overview of the design process down to implementation. A design example of a drawing machine which draws shapes on a screen will run throughout the year with the architectural modelling being covered in this course and RTL modelling, synthesis and implementation (on a Field Programmable Gate Array) in the second semester course. This course focuses primarily on the high-level issues of system modelling, IP core reuse, architecture modelling and simulation.

Programme outcomeUnit learning outcomesAssessment
A2 A3 B1 B2 B3 C2 C5 C6 D4 D5A knowledge and understanding of the process of designing SoC chips.
  • Examination
  • Lab assessment
A2 A3 B1 B2 B3 C2 C5 C6 D4 D5A knowledge and understanding of the industry-standard SystemC hardware description language.
  • Examination
  • Lab assessment
A2 A3 B1 B2 B3 C2 C5 C6 D4 D5An understanding and appreciation of the problems arising out of the rapid change of technology and increase in design complexity.
  • Examination
A2 A3 B1 B2 B3 C2 C5 C6 D4 D5An appreciation of the major architectural and performance factors to be considered in the global design of a large integrated circuit.
  • Examination
  • Lab assessment

Syllabus

Setting the Scene (1): Moore?s law, transistor cost, complexity versus productivity.

Design Hierarchy and System Modelling (1): algorithmic modelling, languages, testing, verification.

Transaction Level Models (2): partitioning system, TLM principles, advantages, disadvantages, different types of TLM for architectural and performance exploration, IP blocks, three layer model.

Introduction to the Drawing Machine (1): computational blocks, channels, testing and environment provided, test bench.

SystemC Hardware Description Language (3): principles, structure, features and syntax, scheduling, untimed TLM of drawing machine.

Translating to a Timed TLM (2): synchronisation, architecture, arbitration, changes to SystemC untimed model.