COMP35112: Chip Multiprocessors (2012-2013)
This is an archived syllabus from 2012-2013
COMP25212 System ArchitectureCo-requisites:
No Co-requisitesCourse Leader: John GurdCourse leader: John GurdAdditional staff: view all staff
||10:00 - 11:00
||15:00 - 16:00
Themes to which this unit belongs
Due to technological limitations, it is proving increasingly difficult to maintain a continual increase in the performance of individual processors. Therefore, the current trend is to integrate multiple processors on to a single chip and exploit the resulting parallel resources to achieve higher computing power. However, this may require significantly different approaches to both hardware and software particularly for general purpose applications. This course will explore these issues in detail.
Trends in technology, limitations and consequences. The move to multi-core
Parallelism in programs, ILP, Thread Level, Data Parallelism.
SIMD, MIMD, Shared Memory, Distributed Memory, strengths & weaknesses.
Multithreaded programming, Data parallel programming, Explicit vs Implicit parallelism, automatic parallelisation. The Case for Shared Memory. When to share?
Shared Memory Multiprocessors
Basic structures, the cache coherence problem. The MESI protocol. Limitations. Directory based coherence.
Programming with Locks & Barriers
The need for synchronisation. Problems with explicit synchronisation
Other Parallel Programming Approaches
MPI & OpenMP
The easy route to automatic parallelisation?
Principles. Hardware & Software approaches
Memory system design. Memory consistency
Other Architectures & Programming Approaches
Data Driven Parallelism
Dataflow principles & Functional Programing