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This is an archived syllabus from 2014-2015

COMP12111 Fundamentals of Computer Engineering syllabus 2014-2015

COMP12111 Fundamentals of Computer Engineering

Level 1
Credits: 10
Enrolled students: 188

Course leader: Paul Nutter

Additional staff: view all staff

Assessment methods

  • 50% Written exam
  • 50% Practical skills assessment
Sem 1 Lecture 1.1 Thu 09:00 - 10:00 -
Sem 1 Lecture 1.1 Mon 16:00 - 17:00 -
Sem 1 w2+ Lab Toot 0 Wed 09:00 - 11:00 X
Sem 1 w2+ Lab Toot 0 Fri 09:00 - 11:00 V
Sem 1 w2+ Lab Toot 1 Fri 09:00 - 11:00 V
Sem 1 w2+ Lab Toot 1 Wed 09:00 - 11:00 X
Sem 1 w2+ Lab Toot 0 Thu 13:00 - 15:00 Z
Sem 1 w2+ Lab Toot 1 Thu 13:00 - 15:00 Z
Sem 1 w2+ Lab Toot 0 Tue 14:00 - 16:00 Y
Sem 1 w2+ Lab Toot 1 Tue 14:00 - 16:00 Y
Sem 1 w2+ Lab Toot 0 Thu 15:00 - 17:00 W
Sem 1 w2+ Lab Toot 1 Thu 15:00 - 17:00 W


This course introduces digital logic and its application in computer organisation and design.

The major emphasis is on practical design work. In the laboratory state-of-the-art computer-aided design tools are used to support the design of digital hardware systems. Students' designs are simulated and then implemented on in-house programmable gate array boards.

The lectures initially support the laboratories but progress to a wider overview of the design and interaction of computer hardware systems. Ultimately a complete - if simple - computer is described.


The main aim of this course is to give students a basic understanding of the hardware which underpins computing systems.

Further aims include:

  • Introduction to basic logic and logic gates
  • Partitioning of simple systems into combinatorial and sequential blocks
  • To introduce basic CAD tools to aid in the design of a basic computer system
  • To provide an overview of hardware description languages with particular emphasis on Verilog
  • Introducing logic level implementation of a simple processor
  • Discussion of how computer systems interact with memory and I/O devices


Basic logic functions (4)

  • Combinatorial logic
  • Sequential logic

Register Transfer Level (3)

Introduction to CAD and Verilog (3)

  • The use of computer aided design to manage complex designs
  • Verilog as a hardware description language

The 'three box' computer model - CPU, Memory and I/O (1)

Processor Design (4)

  • Datapath design
  • Control
  • Optimisation

Memory (3)

  • Types of memory
  • Addressing and interfacing

Input/output (4)

  • Parallel I/O
  • Serial I/O
  • Interrupts and DMA

Teaching methods


22 in total, 2 per week


20 hours in total, 10 2-hour sessions

Feedback methods

Feedback is provided by the automated marking of submitted work. In addition, face-to-face demonstration of submitted work is undertaken for each exercise, where a demonstrator provides one-to-one feedback on the work submitted.

Study hours

  • Assessment written exam (2 hours)
  • Lectures (22 hours)
  • Practical classes & workshops (20 hours)

Employability skills

  • Analytical skills
  • Innovation/creativity
  • Problem solving

Learning outcomes

Programme outcomeUnit learning outcomesAssessment
A3 B3Have an understanding of the hierarchical design of complex digital systems including processors and memory.
  • Lab assessment
  • Examination
A3Have a knowledge of gate-level logic design.
  • Lab assessment
  • Examination
B1 B2 B3Be able to design combinatorial circuits and simple FSMs.
  • Lab assessment
  • Examination
C5 C6Be able to use CAD support tools including design entry via schematic and Verilog, as well as simulation.
  • Lab assessment
A3 B2Understand the operation of a simple processor
  • Lab assessment
  • Examination

Reading list

Digital design with RTL design, Verilog and VHDL (2nd edition)Vahid, Frank9780470531082Wiley2010
Principles of computer hardware (4th edition)Clements, Alan9780199273133Oxford University Press2006
Fundamentals of logic design (7th edition)Roth, Charles H. and Larry L. Kinney9781133628484Cengage Learning2014
Digital design (4th edition)Morris Mano, M. and Michael D. Ciletti9780132340434Pearson2007
Computer systems architecture: a networking approachWilliams, Rob0201648598Addison-Wesley2001

Additional notes

Course unit materials

Links to course unit teaching materials can be found on the School of Computer Science website for current students.