Skip to navigation | Skip to main content | Skip to footer
Menu
Menu

This is an archived syllabus from 2014-2015

COMP35112 Chip Multiprocessors syllabus 2014-2015

COMP35112 Chip Multiprocessors

Level 3
Credits: 10
Enrolled students: 29

Course leader: John Gurd


Additional staff: view all staff

Requisites

  • Pre-Requisite (Compulsory): COMP25212

Assessment methods

  • 75% Written exam
  • 25% Coursework
Timetable
SemesterEventLocationDayTimeGroup
Sem 2 Lecture 1.4 Mon 15:00 - 16:00 -
Sem 2 w19-21,24,32 Lecture 1.4 Thu 10:00 - 11:00 -
Sem 2 w22-23,25-26,30-31 Lab 1.8 Thu 10:00 - 11:00 -
Themes to which this unit belongs
  • Computer Architecture

Overview

Due to technological limitations, it is proving increasingly difficult to maintain a continual increase in the performance of individual processors. Therefore, the current trend is to integrate multiple processors on to a single chip and exploit the resulting parallel resources to achieve higher computing power. However, this may require significantly different approaches to both hardware and software particularly for general purpose applications. This course will explore these issues in detail.

Syllabus

Introduction

Trends in technology, limitations and consequences. The move to multi-coreParallelism in programs, ILP, Thread Level, Data Parallelism.

Parallel Architectures

SIMD, MIMD, Shared Memory, Distributed Memory, strengths and weaknesses.

Parallel Programming

Multithreaded programming, Data parallel programming, Explicit vs Implicit parallelism, automatic parallelisation. The Case for Shared Memory. When to share?

Shared Memory Multiprocessors

Basic structures, the cache coherence problem. The MESI protocol. Limitations. Directory based coherence.

Programming with Locks and Barriers

The need for synchronisation. Problems with explicit synchronisation

Other Parallel Programming Approaches

MPI and OpenMP

Speculation

The easy route to automatic parallelisation?

Transactional Memory

Principles. Hardware and Software approaches

Memory Issues

Memory system design. Memory consistency

Other Architectures and Programming Approaches

GPGPUs, CUDA

Data Driven Parallelism

Dataflow principles and Functional Programing

Feedback methods

Written feedback on reports for laboratory exercises. Students who attempt previous exam questions can get feedback on their answers.

Study hours

  • Lectures (24 hours)

Employability skills

  • Analytical skills
  • Problem solving
  • Written communication
  • Other

Learning outcomes

Learning outcomes are unknown for COMP35112.

Reading list

COMP35112 does not have a specified reading list.

Additional notes

Course unit materials

Links to course unit teaching materials can be found on the School of Computer Science website for current students.