COMP35112 Chip Multiprocessors syllabus 2015-2016
Due to technological limitations, it is proving increasingly difficult to maintain a continual increase in the performance of individual processors. Therefore, the current trend is to integrate multiple processors on to a single chip and exploit the resulting parallel resources to achieve higher computing power. However, this may require significantly different approaches to both hardware and software particularly for general purpose applications. This course will explore these issues in detail.
Trends in technology, limitations and consequences. The move to multi-coreParallelism in programs, ILP, Thread Level, Data Parallelism.
SIMD, MIMD, Shared Memory, Distributed Memory, strengths and weaknesses.
Multithreaded programming, Data parallel programming, Explicit vs Implicit parallelism, automatic parallelisation. The Case for Shared Memory. When to share?
Shared Memory Multiprocessors
Basic structures, the cache coherence problem. The MESI protocol. Limitations. Directory based coherence.
Programming with Locks and Barriers
The need for synchronisation. Problems with explicit synchronisation
Other Parallel Programming Approaches
MPI and OpenMP
The easy route to automatic parallelisation?
Principles. Hardware and Software approaches
Memory system design. Memory consistency
Other Architectures and Programming Approaches
Data Driven Parallelism
Dataflow principles and Functional Programing
Written feedback on reports for laboratory exercises. Students who attempt previous exam questions can get feedback on their answers.
- Lectures (24 hours)
- Analytical skills
- Problem solving
- Written communication
Learning outcomes are unknown for COMP35112.
COMP35112 does not have a specified reading list.
Course unit materials
Links to course unit teaching materials can be found on the School of Computer Science website for current students.