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COMP22111 Processor Microarchitecture syllabus 2018-2019

COMP22111 materials

COMP22111 Processor Microarchitecture

Level 2
Credits: 10
Enrolled students: 49

Course leader: Paul Nutter


Additional staff: view all staff

Requisites

  • Pre-Requisite (Compulsory): COMP12111

Additional requirements

  • Students who are not from the School of Computer Science must have permission from both Computer Science and their home School to enrol.

Assessment methods

  • 55% Written exam
  • 45% Coursework
Timetable
SemesterEventLocationDayTimeGroup
Sem 1 Lecture 1.4 Tue 09:00 - 10:00 -
Sem 1 w1-5,7-11 Lecture 1.3 Thu 14:00 - 15:00 -
Sem 1 w3+ Lab Toot 1 Fri 14:00 - 16:00 H
Sem 1 w3+ Lab Toot 1 Thu 16:00 - 18:00 F
Sem 1 w11 Lecture IT407 Fri 13:00 - 14:00 -
Themes to which this unit belongs
  • System-on-Chip

Overview

This module aims to develop the two key aspects of COMP12111, namely hardware design and microprocessors. COMP12111 gave an overview of the hardware development process; COMP22111 builds on these skills to introduce and exercise industrially relevant hardware skills with a design flow from concept to implementation. It used microprocessors as design examples to illustrate and reinforce how machine code, output from a compiler, is interpreted and executed by a computer.

Much of the emphasis is on practical work and the laboratories take a microprocessor design through from an instruction set specification to a physical FPGA implementation. The lectures complement this and extend the scope towards the processes necessary to turn this into custom silicon.

Aims

The module aims to give a view of the role of a digital hardware designer, taking an idea and implementing it as a silicon chip. A processor is a representative example of logic used in today's chips, also giving further insight into how computers actually work.

Having completed the module you should have developed the confidence to be able to take a concept and realise it in hardware. You should also appreciate the test and verification processes involved so that your chips work efficiently and reliably ... first time, every time!

Syllabus

1. Introduction (1 lecture)
Overview, introduction to the lab, approaches to design and the management of complexity

2. Instruction Set Architectures (2 lectures)
RISC v CISC, recap of MU0, Stump ISA, other architectures

3. Review of sequential systems (2 lectures)
The processor as a sequential system, datapath and control, register transfer level (RTL) design, Mealy and Moore finite state machines.

4. Advanced Verilog (3 lectures)
Verilog recap, tasks and functions, structural Verilog, verification & testing in Verilog, the Verilog simulator.

5. Designing and Implementing Processors (2 lectures)
Implementation of processors from the ISA, architectural design, RTL design, Verilog implementation. 

6. Improving Processor Performance (1 lecture)
Superscalar, multicore and pipelining, examples of processor speedup, hazards.

7. Specialised Processing Architectures (1 lecture)
Examining DSPs, floating-point (and other) coprocessors, SIMD and vector extensions as well as VLIW.

8. Microarchitectural Structures (1 lecture)
Basic building blocks, including register files, FIFOs, RAMs, CAMs, arithmetic circuits (adders and multipliers) and shifters.

9. FPGAs (1 lecture)
FPGA mode of operation and its spatial programming model as well as application examples.

10. Hardware Design Examples (1 lecture)
Investigating a few circuits (e.g., digital filters, sorters, PWMs) and understanding their design factors.

11. Electronics (1 lecture)
Ohm's and Kirchhoff's laws; inverters, NAND and NOR gates; MOS transistors and CMOS technology design factors.

12. Technology (1 lecture)
Standard Cell design methodology, PLA, Multiplexer, look-up table technology.

13. Computer Aided Design (CAD) Tools (1 lecture)
Logic synthesis, constraints, Place & Route, DRCs.

14. Verification and Test (1 lecture)
Analogue and digital simulation, regression testing, production test and yield built-in self-test (BIST).

15. Timing and Clocking (1 lecture)
System performance, setup and hold times, jitter, clock skew, clock distribution networks, propagation delay, signal integrity, static timing analysis (STA), clock domains, synchronisation and meta-stability.

16. Hardware Security (1 lecture) 
Understanding hardware related vulnerabilities (Spectre, Meltdown, RowHammer) and countermeasures. DPA and other forms of side-channel attacks 

17. Future (1 lecture)
Limits of Moores' law, understanding the importance of energy efficiency, new manufacturing techniques, memristor-based computing, exotic technologies (Quantum dots, Graphene, Spintronics, etc.).

Teaching methods

Lectures

22

Laboratories

20 hours in total

Feedback methods

Direct feedback comes from laboratory work, both from working with the tools themselves and from the staff. Development results can (and should) be observed throughout using simulation and test. Final results are observable with a hardware realisation.

Less formal feedback is available at all times, especially during lectures and laboratory sessions.

Study hours

  • Assessment written exam (2 hours)
  • Lectures (11 hours)
  • Practical classes & workshops (22 hours)

Employability skills

  • Analytical skills
  • Innovation/creativity
  • Problem solving
  • Other

Learning outcomes

Programme outcomeUnit learning outcomesAssessment
A1Explain the operation of sequential systems and design and implement systems consisting of datapath and control elements.
A1Apply design methodologies to aid in the design of complex digital systems.
A1Discuss key features of the Verilog language and be able to implement sequential digital systems at the register transfer level (RTL) of the design hierarchy.
A1Explain the design factors of Instruction Set Architectures and discuss the differences between RISC and CISC CPUs, identifying the key functional components and explaining how they work together to execute instructions.
A1 D5Explain the stages of processor design starting from the Instruction Set Architecture with respect to implementing designs in Verilog.
A1Discuss approaches for the testing of complex digital designs and apply these to test digital designs implemented in Verilog.
A1Identify techniques for improving CPU performance including pipelining, superscalar processing and multicore.
A1Analyse how design factors such as scaling, monetary cost, performance and power consumption impact VLSI designs.
A1Describe examples of specialised compute units such as coprocessors, floating-point units and vector extensions and identify their relative advantages and disadvantages.
A1Compare different processor technologies, such as CPU, GPU and FPGA, with respect to different application domains, and discuss future industry trends beyond traditional CMOS scaling.
A1Reveal important parts of the CAD tool stack including logic synthesis and test as well as placement and routing algorithms.

Reading list

TitleAuthorISBNPublisherYearCore
Verilog hardware description language (5th edition)Thomas, Donald and Philip Moorby9780387849300Springer2008

Additional notes

Course unit materials

Links to course unit teaching materials can be found on the School of Computer Science website for current students.