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COMP22111 Processor Microarchitecture syllabus 2017-2018

COMP22111 materials

COMP22111 Processor Microarchitecture

Level 2
Credits: 10
Enrolled students: 61

Course leader: Paul Nutter


Additional staff: view all staff

Requisites

  • Pre-Requisite (Compulsory): COMP12111

Additional requirements

  • Students who are not from the School of Computer Science must have permission from both Computer Science and their home School to enrol.

Assessment methods

  • 55% Written exam
  • 45% Coursework
Timetable
SemesterEventLocationDayTimeGroup
Sem 1 Lecture 1.3 Mon 12:00 - 13:00 -
Sem 1 w1 Lecture 1.3 Thu 14:00 - 15:00 -
Sem 1 w2-5,7-12 Lecture 1.5 Tue 09:00 - 10:00 -
Sem 1 w3+ Lab Toot 1 Tue 10:00 - 12:00 H
Sem 1 w3+ Lab Toot 1 Thu 11:00 - 13:00 F
Themes to which this unit belongs
  • System-on-Chip

Overview

This module aims to develop the two key aspects of COMP12111, namely hardware design and microprocessors. COMP12111 gave an overview of the hardware development process; COMP22111 builds on these skills to introduce and exercise industrially relevant hardware skills with a design flow from concept to implementation. It used microprocessors as design examples to illustrate and reinforce how machine code, output from a compiler, is interpreted and executed by a computer.

Much of the emphasis is on practical work and the laboratories take a microprocessor design through from an instruction set specification to a physical FPGA implementation. The lectures complement this and extend the scope towards the processes necessary to turn this into custom silicon.

Aims

The module aims to give a view of the role of a digital hardware designer, taking an idea and implementing it as a silicon chip. A processor is a representative example of logic used in today's chips, also giving further insight into how computers actually work.

Having completed the module you should have developed the confidence to be able to take a concept and realise it in hardware. You should also appreciate the test and verification processes involved so that your chips work efficiently and reliably ... first time, every time!

Syllabus

Introduction (2)

Scales of integration, CMOS versus other technologies, VLSI trends, overview of top down design hierarchy, VLSI design route.

Verilog Hardware Description Language (4)

Principles, structure, features and syntax, scheduling and parallelism, hierarchical structures; test benches.

The STUMP - an example RISC(2)

RISC versus CISC, load/store architecture, non-pipelined behaviour, instruction set.

An example CISC (1)

A look at a CISC instruction set as a point of comparison.

Architectural Design of STUMP (1)

Block partitioning, datapath occupancy.

Register Transfer Level Design (1)

Formation of a STUMP datapath.

Finite State Machines (1)

The application of FSMs and their implementation in Verilog.

Design Flows (1)

CAD tools from concept to (working) chip.

Verification and Testing (1)

Modelling and testing designs at different levels of abstraction, yields and testing chips, test coverage.

Timing and Clocking (1)

Clock generation, buffering, and distribution; crossing clock domains.

Technology (1)

VLSI structures, standard cells, macrocells, ASICs and FPGAs.

Teaching methods

Lectures

22

Laboratories

20 hours in total

Feedback methods

Direct feedback comes from laboratory work, both from working with the tools themselves and from the staff. Development results can (and should) be observed throughout using simulation and test. Final results are observable with a hardware realisation.

Less formal feedback is available at all times, especially during lectures and laboratory sessions.

Study hours

  • Assessment written exam (2 hours)
  • Lectures (11 hours)
  • Practical classes & workshops (22 hours)

Employability skills

  • Analytical skills
  • Innovation/creativity
  • Problem solving
  • Other

Learning outcomes

Programme outcomeUnit learning outcomesAssessment
A3Have a knowledge and understanding of the process of designing VLSI chips.
  • Examination
  • Lab assessment
A3Have an understanding of the different design stages and representations of a VLSI circuit.
  • Examination
  • Lab assessment
A3Have an understanding of the major architectural and performance factors to be considered in the global design of a large integrated circuit.
  • Examination
A3Have an understanding and appreciation of the problems arising out of the rapid change of technology and increase in design complexity.
  • Examination
A3 B1 B2 B3 C1 C2 C5 C6 D4 D5Be able to design a 16-bit RISC processor at the upper levels of the design process, and have experience of the tools to test and debug the design.
  • Lab assessment
  • Examination
A3 C5 C6Have a knowledge and understanding of industry-standard hardware description languages.
  • Lab assessment
  • Examination

Reading list

COMP22111 does not have a specified reading list.

Additional notes

Course unit materials

Links to course unit teaching materials can be found on the School of Computer Science website for current students.