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Current postgraduate taught students

COMP60042: Low-Power System Design (2007-2008)

This is an archived syllabus from 2007-2008

Low-Power System Design
Level: 6
Credit rating: 15
Pre-requisites: No Pre-requisites
Co-requisites: No Co-requisites
Duration: 80 hours: on-line self-study material supported by unsupervised practical exercises and seminar sessions
Lectures: 1 day per week (5 weeks), but no scheduled slot - this is a self-study course.
Examples classes: Seminar sessions will be arranged during each of the 5 weeks to discuss problems, progress, etc.
Labs: The practical sessions provide hands-on experience with the ARM Developer Suite.
Lecturers: Steve Furber
Course lecturer: Steve Furber

Additional staff: view all staff
This is a distance learning course with flexible self-study offered in Sem 1 w7-11.
Assessment Breakdown
Exam: 33%
Coursework: 66%
Lab: 0%


This course covers the design of low-power embedded systems based around the ARM 32-bit microprocessor core. It will be taught primarily through self-study on-line material, supported by seminars and practical exercises.


Computing is becoming increasingly mobile, both in recognisable forms such as lap-top computers and in forms where the computing function is concealed such as digital mobile telephones. Mobile computing increases significantly the importance of minimising the power consumed by the system as excessive consumption directly compromises battery life. The aim of this course is to introduce students to the practical aspects of engineering high-performance computer systems where power consumption is a major consideration at every stage of the design. The course is heavily based around the ARM 32-bit RISC microprocessor, a world-leading processor for power-sensitive applications, and covers many aspects of designing power-efficient systems around ARM cores.

Learning Outcomes

A student completing this course unit should have achieved:
1. an understanding of the principles of the ARM and Thumb instruction sets and their practical use. (A)

2. an understanding of the principles of low-power RISC processor design. (A)

3. an insight into the design of memory hierarchies for power-efficient systems, and an ability to apply a systematic methodology to memory hierarchy design. (A and C)

4. an overview of the system-level issues involved in designing a particular power-sensitive application. (B)

5. an ability to write clear and concise reports on matters relating to low-power design. (D)

Assessment of Learning outcomes

Learning outcomes (1), (2) and (4) are assessed by examination,
learning outcome (3) by examination and in the laboratory and
learning outcome (5) by the coursework.

Contribution to Programme Learning Outcomes

A1, A2, B2, C1, D3


Basics of processor design.
Processor design trade-offs.
The ARM and Thumb instruction sets in outline.
The ARM instruction set in detail.
Exceptions and special instructions.
The Thumb instruction set in detail.
ARM integer cores.
Memory hierarchy.
The ARM memory management and memory protection units.
System development.
On-chip buses.
On-chip debug.

Special Resources Needed to complete the module

The ARM CBT (computer-based training package) contains the basic course material - this is available on-line.
Access to the ARM Developer Suite (ADS) is required for the practicals and the post-course work. This runs on Windows PCs and is available on School machines. We can provide remote access to suitable School machines. Alternatively, a (limited-time) demo version may be available for part-time students wishing to take the course.

Reading List

1. Access to the course book is highly desirable: Furber, ARM System-on-Chip Architecture. Addison-Wesley, 2000.

2. Full course material, including the laboratory manual, are supplied on-line.

Core Text
Title: ARM system-on-chip architecture (2nd edition)
Author: Furber, Steve
ISBN: 0201675196
Publisher: Addison Wesley
Edition: 2nd
Year: 2000