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Current postgraduate taught students

COMP60062: System Level Design (2007-2008)

This is an archived syllabus from 2007-2008

System Level Design
Level: 6
Credit rating: 15
Pre-requisites: No Pre-requisites
Co-requisites: No Co-requisites
Lecturers: Linda Brackenbury
Course lecturer: Linda Brackenbury

Additional staff: view all staff
Sem 2 w19-25,29-32 Lecture PEVELab Fri 09:00 - 11:00 -
Sem 2 w19-25,29-32 Lab ECS Fri 10:00 - 12:00 -
Sem 2 w19-25,29-32 Lecture PEVELab Fri 12:00 - 13:00 -
Sem 2 w19-25,29-32 Lab ECS Fri 14:00 - 17:00 -
Assessment Breakdown
Exam: 33%
Coursework: 67%
Lab: 0%


The design of a modern System-on-Chip (SoC) is a complex task involving a range of skills and a deep understanding of a hierarchy of perspectives on design, from processor architecture down to signal integrity. This course will provide insights into these processes, focussing primarily on the high-level issues of system modelling, IP core reuse, architecture modelling and testing, on-chip interconnect, and RTL synthesis.


This course unit aims to introduce the main tools and techniques employed at the
higher levels of complex SoC design, to provide an overview of the design process

Learning Outcomes

A student completing this course unit should:

have knowledge and understanding of the principle tools used in system-level design

understand issues relating to on-chip interconnect, architecture modelling and testing, and design verification

understand the role of RTL synthesis, technology mapping, cell libraries and timing closure in the SoC design process

be able to apply this understanding to the design of prototype systems

have insights into future developments in SoC technology

Assessment of Learning outcomes

Learning outcomes A1, A2, B2, B3 are assessed by examination,
learning outcomes A1, A2, B2, B3, D1 are assessed by team presentations and learning outcomes A1, A2, B2, B3, D3 are assessed by laboratory reports.

Contribution to Programme Learning Outcomes

A1, A2, B2, B3, C1, D1, D3


What do you want? [4]
Specifications, system modelling with System C, IP blocks,
cores, on-chip interconnect (buses and Networks-on-Chip).

How do you design it? [4]
Architecture modelling and testing, tools and flows, verification.

Implementation. [4]
RTL synthesis, Verilog, design-for-test, low-power-design,
technology mapping, cell libraries, principles of tools, FPGAs.

Getting it to work. [4]
Debugging, timing closure, asynchronous design & GALS.

Where is it all going? [2]
The future of SoC design: reconfigurability, chip multiprocessors.

Feedback. [2]
Team presentations, working system demos.


The lab is centred around the design and implementation of a drawing machine.
Participants will gain experience of using industry-standard CAD tools together with commonly used hardware description languages, as well as implementing their design on a field programmable Gate Array and drawing shapes on a monitor screen.

Reading List

Special resources are needed in this course unit.

Various specialist CAD tools are used in the course including laboratory: System C.