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COMP12111 Fundamentals of Computer Engineering syllabus 2021-2022

COMP12111 materials

COMP12111 Fundamentals of Computer Engineering

Level 1
Credits: 10
Enrolled students: 493

Course leader: Paul Nutter


Additional staff: view all staff

Additional requirements

  • Students who are not from the School of Computer Science must have permission from both Computer Science and their home School to enrol.

Assessment methods

  • 50% Written exam
  • 50% Practical skills assessment
Timetable
SemesterEventLocationDayTimeGroup
Sem 1 w1-5,7-11 Lecture Engineering Building A 2A.041 Lecture Theatre A Mon 12:00 - 13:00 -
Sem 1 w2-5,7-12 DROP-IN 1.8+1.10 Wed 09:00 - 11:00 -
Sem 1 w2-5,7-12 DROP-IN 1.8+1.10 Mon 13:00 - 15:00 -
Sem 1 w2-5,7-12 DROP-IN 2.25 (A+B) Thu 13:00 - 15:00 -
Sem 1 w2-5,7-12 DROP-IN 2.25 (A+B) Tue 15:00 - 17:00 -

Overview

In this course you will learn about the design of electronic systems from simple digital circuits to the design of a simple processor.

The major emphasis is on practical design work, the taught material is supported by practical laboratory exercises where you get to put the concepts you have learnt into practice.

Aims

The main aim of this course is to give students a basic understanding of the hardware which underpins computing systems.

Further aims include:

  • Introduction to basic logic and logic gates
  • Partitioning of simple systems into combinatorial and sequential blocks
  • To introduce basic CAD tools to aid in the design of a basic computer system
  • To provide an overview of hardware description languages with particular emphasis on Verilog
  • Introducing logic level implementation of a simple processor
  • Discussion of how computer systems interact with memory and I/O devices

Syllabus

  • Introduction to logic

Digital signals, data representation, Boolean logic and functions, De Morgan’s theorem, logic gates, multiplexers, binary arithmetic, abstraction & hierarchy, clocks, sequential systems.

  • Computer Aided Design (CAD)

Complexity and design – the need for CAD tools, testing & simulation,

  • Hardware description languages - Verilog

Introduction to Verilog, Verilog assignments, the always block and sensitivity list, design of combinatorial and sequential circuits in Verilog.

  • Register Transfer Level (RTL) Design

The synchronous paradigm, introduction to sequential systems, RTL view of design, the register, datapath and control,

  • Finite State Machines (FSM)

Introduction to the FSM, state transition diagrams, state transition tables, implementation in Verilog.

  • Processor Design

Overview of the three-box model: CPU, Memory, I/O, processor operation, instruction execution – fetch/decode/execute – and the sequencing of actions, program counter, instruction register, condition code register.

  • The Manchester University 0 (MU0) Processor

Introduction to MU0 - instruction set and operation, arithmetic logic unit (ALU) design and critical path, design of the MU0 datapath and control.

  • Memory

Von Neumann and Harvard architecture, tri-state buffers and bidirectional buses, memory map, address decoding schemes – one dimensional and two-dimensional, address decoders. Memory hierarchy

  • Input and output

The I/O interface, communication and I/O devices,

  • More Verilog

Examples of circuit designs in Verilog

  • Programming MU0

Programming MU0 and accessing peripherals

 

Teaching methods

This unit will be delivered using a blended approach to learning. Self-study materials will be made available in the form of written notes, videos and self-assessment quizzes in Blackboard that allow you to check your understanding of the material provided. Each week there will be a live session which will focus on covering design examples and/or providing support and general feedback on laboratory exercises. These sessions will be, where possible, interactive.

 

Laboratory exercises are supported by weekly drop-in sessions (from week 2), where students can get help and support.

 

Students are expected to spend (approximately):

 

2 hours per week working on the online asynchronous material (22 hours in total).

5 hours per week on the laboratory exercises (45 hours in total).

1 hour per week synchronous lecture (11 hours in total).

Feedback methods

Feedback is provided via formative quizzes in Blackboard and via automated marking for laboratory work, with feedback on work being delivered by email.

Study hours

  • Assessment written exam (2 hours)
  • Lectures (11 hours)

Employability skills

  • Analytical skills
  • Innovation/creativity
  • Problem solving

Learning outcomes

On successful completion of this unit, a student will be able to:

  • Convert between different number bases and perform the process of binary addition and subtraction.
  • Manipulate Boolean expressions and illustrate their implementation using simple combinatorial circuits.
  • Discuss the design of simple binary adders and highlight the imitations of the design.
  • Explain the key features of the Verilog language and write behavioural models in Verilog of combinatorial and sequential logic circuit designs.
  • Design, implement and verify circuit designs using CAD tools.
  • Discuss the organisation and operation of a simple digital computer including the processor, memory and input/output.
  • Discuss and implement the design of a simple processor.
  • Discuss the execution of machine language programs on a simple processor design and produce working code.

Reading list

TitleAuthorISBNPublisherYear
Principles of computer hardware Clements, Alan, 1948-9780199273133Oxford University2006.
Quick start guide to Verilog LaMeres, Brock J.,9783030105525; 3030105520; 9783030105532; 3030105539Springer[2019]
Digital design.Mano,M. Morris, 9780132774208Prentice Hall2011
Fundamentals of logic design Roth, Charles H., 1932-9781133628484Nelson Engineering2013.
The Verilog hardware description language /Thomas, D. E.9780387849300 (hbk.) :Springerc2008.
Digital design : with RTL design, VHDL, and Verilog Vahid, Frank.9780470531082Wileyc2011.
Computer systems architecture : a networking approach Williams, Rob.0201648598Addison-Wesleyc2001.
Computer systems architecture : a networking approach Williams, Rob, 1948-9780321340795Pearson Prentice Hall2006.

Additional notes

Course unit materials

Links to course unit teaching materials can be found on the School of Computer Science website for current students.