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COMP35212: High Performance Microprocessors Architectures (2010-2011)

This is an archived syllabus from 2010-2011

High Performance Microprocessors Architectures
Level: 3
Credit rating: 10
Pre-requisites: COMP10031 and COMP20051
Co-requisites: No Co-requisites
Duration: 11 weeks
Lectures: 22
Lecturers: John Gurd
Course lecturer: John Gurd

Additional staff: view all staff
Sem 2 Lecture 1.4 Tue 13:00 - 14:00 -
Sem 2 Lecture 1.4 Mon 13:00 - 14:00 -
Assessment Breakdown
Exam: 100%
Coursework: 0%
Lab: 0%

Themes to which this unit belongs
  • Computer Architecture


It is perfectly possible to write programs and get them to work without much detailed understanding of either (1) how a compiler turns the source code into machine code, or (2) how a computer executes the machine code. However, to make the resulting program run quickly (perform well), such an understanding is essential. This course provides the necessary material in the context of modern microprocessor designs. The course is based on the renowned book "Computer Architecture - A Quantitative Approach" by John Hennessy and David Patterson.


Modern computer systems are almost exclusively constructed from single-chip microprocessors, increasingly now with multiple core Central Processing Units. As fabrication density and integration levels have increased, microprocessor manufacturers have adopted many of the architectural ideas first devised for the previous generations of high-performance computers. The aim of this course is to provide a thorough understanding of the machine architectural and associated compilation techniques used in current microprocessors and to examine their performance characteristics. Advanced techniques, which may find their way into the next generation of products, are also examined and analysed.

Programme outcomeUnit learning outcomesAssessment
A3Have an understanding of trends in the development of microprocessor systems.
  • Examination
A3Have knowledge of the techniques used to benchmark modern computer systems.
  • Examination
A3 B1 B2 B3Understand the techniques used in microprocessor micro-architecture and be able to produce designs of the elements of a processor core.
  • Examination
A3 B1 B2 B3Understand the structure of memory hierarchy in modern microprocessor systems and be able to produce designs of such systems.
  • Examination
A3Have an understanding of future trends in microprocessor technology and how these are likely to affect the development of computer systems.
  • Examination


Introduction [2]

Trends in technology, cost and computer usage. Measuring and reporting performance; benchmarking and benchmarks.

Instruction Level Parallelism [8]

Instruction pipelining. Data hazards, dynamic scheduling. Branch prediction: static, dynamic. Zero-cycle branches. Multiple instruction issue implementations. Compiling for superscalar implementations. Hardware support for instruction level parallelism.

Memory Hierarchy [6]

Cache memory: block organization; cache line placement, replacement and write policies. Write buffering. Classifying misses: compulsory/capacity/conflict misses. Reducing misses: line size, associativity, victim cache, prefetching, compiler optimizations. Reducing miss penalty: reordering memory cycles, subblock placement, early restart, lockup-free operation, multilevel caches. Reducing hit time. Main memory and its performance.

Case Studies [2]

Intel Pentium Pro - Superscalar RISC implementation of a CISC instruction set. Dec Alpha - a 'clean-sheet' superscalar RISC architecture. PowerPC - a pragmatic combination of features.

Multicore Chips [2]

The trend to multicore; anticipated `roadmap'. Specifics of Intel Core Duo and Quad chips.

The Future [2]

Future technology limitations. The requirement for Mobile code; JAVA implementation techniques, JIT compilation. Dynamic optimizations. Virtualization.

Reading List

The recommended text (see below) is for reference only; it is the most famous book on computer architecture. There is no need to buy a copy unless you intend to make a career out of microprocessor design. The overnight loan library has three copies of the third edition and one copy of the fourth edition.

Core Text
Title: Computer architecture: a quantitative approach (5th edition)
Author: Hennessy, John L. and David A. Patterson
ISBN: 9780123838728
Publisher: Morgan Kaufmann
Edition: 5th
Year: 2011
The latest edition of "the computer architect's bible". A comprehensive reference work covering all aspects of modern microprocessor architecture. Not necessary to own unless you are a committed computer architect.