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Current postgraduate taught students

COMP60632: Future Multi-Core Computing (2011-2012)

This is an archived syllabus from 2011-2012

Future Multi-Core Computing
Level: 6
Credit rating: 15
Pre-requisites: No Pre-requisites
Co-requisites: No Co-requisites
Lecturers: Mikel Lujan
Course lecturers: Pete Jinks

Mikel Lujan

Additional staff: view all staff
Sem 2 P3 Lecture APEcs Suite Mon 09:00 - 17:00 -
Assessment Breakdown
Exam: 50%
Coursework: 50%
Lab: 0%

Themes to which this unit belongs
  • Parallel Computing in the Multi-core Era


Dual-core and Quad-core processors are now becoming commonplace as circuit limits are reached which prevent further performance gains from simple clock-speed increases. Major industrial projections expect processors with hundreds of cores within a few years. But, current hardware architectural approaches are not applicable to the scale of these future processors. In addition, programming techniques, required to write general purpose parallel programs to make effective use of these systems, are regarded as inadequate. These are therefore very active research areas and there are a number of different but inter-related directions being explored. The purpose of this course unit is to study that research by a combination of directed reading and practical experimentation with state-of-the art multi-core hardware, simulators of research systems and novel language implementations.


The unit aims to study the technological issues which will determine both the future hardware architecture and the programming techniques which will be necessary to extract performance from multi-core processors. It will examine the limitations of current approaches and study in detail those areas of research which are most likely to provide solutions.

Learning and Teaching Processes

Introductory material will be provided by a small number of traditional lectures. The majority of the research material will be covered by directed reading followed by small group presentation and discussion. Practical work will take the form of small group projects where a student will be expected to investigate a particular topic in depth by experiment.

Programme outcomeUnit learning outcomesAssessment
G1Understand the limitations of current multi-core computing. Have detailed knowledge of those areas of research that are intended to address both the hardware architecture and programming approaches which will be needed to develop future high performance multi-core systems.
G1 G2Be able to analyse current research in the multi-core area with the ability to judge whether they are promising in the context of the technological limitations which constrain progress.
G1 G2 G3Be able to access the parallel potential of multi-core systems both by the use of real hardware and simulation. Be able to develop parallel programs for multi-core systems using novel programming approaches.
G2 G3 G4Be able to evaluate research by literature study. Be able to perform research level presentations. Small group working skills.

Reading List

Core Text
Title: Computer architecture: a quantitative approach (5th edition)
Author: Hennessy, John L. and David A. Patterson
ISBN: 9780123838728
Publisher: Morgan Kaufmann
Edition: 5th
Year: 2011

Supplementary Text
Title: Memory system: you can't avoid it, you can't ignore it, you can't fake it
Author: Jacob, Bruce
ISBN: 9781598295870
Publisher: Morgan & Claypool
Year: 2008

Supplementary Text
Title: Memory systems: cache, DRAM, disk
Author: Jacob, Bruce and Spencer W. Ng and David T. Wang
ISBN: 9780123797513
Publisher: Morgan Kaufmann
Year: 2008

Supplementary Text
Title: Computer architecture techniques for power-efficiency
Author: Kaxiras, Stefanos and Margaret Martonosi
ISBN: 9781598292084
Publisher: Morgan & Claypool
Year: 2008

Supplementary Text
Title: Java concurrency in practice
Author: Goetz, Brian et al
ISBN: 9780321349606
Publisher: Addison Wesley
Year: 2015

Supplementary Text
Title: Transactional memory (2nd edition)
Author: Harris, Tim and James Larus and Raji Rajwar
ISBN: 9781608452354
Publisher: Morgan & Claypool
Edition: 2nd
Year: 2010

Supplementary Text
Title: On-chip networks
Author: Jerger, Natalie D. Enright and Li-Shiuan Peh
ISBN: 9781598295849
Publisher: Morgan & Claypool
Year: 2009

Supplementary Text
Title: Art of multiprocessor programming (revised 1st edition)
Author: Herlihy, Maurice and Nir Shavit
ISBN: 9780123973375
Publisher: Morgan Kaufmann
Edition: rev 1st
Year: 2012

Supplementary Text
Title: Principles and practices of interconnection networks
Author: Dally, William James and Brian Patrick Towles
ISBN: 9780122007514
Publisher: Morgan Kaufmann
Year: 2004

Supplementary Text
Title: On-chip communication architectures: system on chip interconnect
Author: Pasricha, Sudeep and Nikil Dutt
ISBN: 9780123738929
Publisher: Morgan Kaufmann
Year: 2008