This is an archived syllabus from 2013-2014
COMP22111 Processor Microarchitecture syllabus 2013-2014
COMP22111 Processor Microarchitecture
Enrolled students: 40
Course leader: Paul Nutter
Additional staff: view all staff
- Pre-Requisite (Compulsory): COMP12111
- 55% Written exam
- 45% Coursework
|Sem 1||Lecture||LF15||Mon||12:00 - 12:00||-|
|Sem 1 w1-5,7-11||Lecture||1.4||Thu||14:00 - 14:00||-|
|Sem 1 w1-2||Lecture||LF15||Tue||10:00 - 10:00||-|
|Sem 1 w3+||Lab||Toot 0||Tue||10:00 - 10:00||-|
|Sem 1 w3+||Lab||Toot 1||Tue||10:00 - 10:00||-|
This module aims to develop the two key aspects of COMP12111, namely hardware design and microprocessors. COMP12111 gave an overview of the hardware development process; COMP22111 builds on these skills to introduce and exercise industrially relevant hardware skills with a design flow from concept to implementation. It used microprocessors as design examples to illustrate and reinforce how machine code, output from a compiler, is interpreted and executed by a computer.
Much of the emphasis is on practical work and the laboratories take a microprocessor design through from an instruction set specification to a physical FPGA implementation. The lectures complement this and extend the scope towards the processes necessary to turn this into custom silicon.
The module aims to give a view of the role of a digital hardware designer, taking an idea and implementing it as a silicon chip. A processor is a representative example of logic used in today's chips, also giving further insight into how computers actually work.
Having completed the module you should have developed the confidence to be able to take a concept and realise it in hardware. You should also appreciate the test and verification processes involved so that your chips work efficiently and reliably ... first time, every time!
Scales of integration, CMOS versus other technologies, VLSI trends, overview of top down design hierarchy, VLSI design route.
Verilog Hardware Description Language (4)
Principles, structure, features and syntax, scheduling & parallelism, hierarchical structures; test benches.
The STUMP - an example RISC(2)
RISC versus CISC, load/store architecture, non-pipelined behaviour, instruction set.
An example CISC (1)
A look at a CISC instruction set as a point of comparison.
Architectural Design of STUMP (1)
Block partitioning, datapath occupancy.
Register Transfer Level Design (1)
Formation of a STUMP datapath.
Finite State Machines (1)
The application of FSMs and their implementation in Verilog.
Design Flows (1)
CAD tools from concept to (working) chip.
Verification and Testing (1)
Modelling and testing designs at different levels of abstraction, yields and testing chips, test coverage.
Timing and Clocking (1)
Clock generation, buffering, and distribution; crossing clock domains.
VLSI structures, standard cells, macrocells, ASICs and FPGAs.
20 hours in total
Feedback methodsDirect feedback comes from laboratory work, both from working with the tools themselves and from the staff. Development results can (and should) be observed throughout using simulation and test. Final results are observable with a hardware realisation.
Less formal feedback is available at all times, especially during lectures and laboratory sessions.
- Assessment written exam (2 hours)
- Lectures (11 hours)
- Practical classes & workshops (22 hours)
- Analytical skills
- Problem solving
On successful completion of this unit, a student will be able to:
Learning outcomes are detailed on the COMP22111 course unit syllabus page on the School of Computer Science's website for current students.
|ARM system-on-chip architecture /||Furber, Stephen B.||0201675196||Addison-Wesley, an imprint of Pearson Education,||2000.|
|Principles of computer hardware||Clements, Alan, 1948-||9780199273133||Oxford University||2006.|
|The Verilog hardware description language /||Thomas, D. E.||9780387849300 (hbk.) :||Springer||c2008.|
Course unit materials
Links to course unit teaching materials can be found on the School of Computer Science website for current students.