This is an archived syllabus from 2013-2014
COMP32212 Implementing System-on-Chip Designs syllabus 2013-2014
COMP32212 Implementing System-on-Chip Designs
Level 3
Credits: 10
Enrolled students: 17
Course leader: Jim Garside
Additional staff: view all staff
Requisites
- Pre-Requisite (Compulsory): COMP22111
- Pre-Requisite (Compulsory): COMP32111
Additional requirements
COMP32111 unavailable 2013/4.
Assessment methods
- 50% Written exam
- 50% Practical skills assessment
| Semester | Event | Location | Day | Time | Group |
|---|---|---|---|---|---|
| Sem 2 | Lecture | LF17 | Tue | 15:00 - 15:00 | - |
| Sem 2 | Lab | Toot 0 | Tue | 16:00 - 16:00 | - |
- System-on-Chip
Overview
The ultimate goal of any hardware design is a physical implementation. This course complements COMP32111 by examining the process of realising a design in hardware. The practical part of the course develops higher level models into Verilog HDL and thence to an FPGA. In the lectures the process of mapping designs to ASICs is studied with emphasis on practicalities such as trading chip area, delays, power, etc. to meet a specification. Emphasis is also given to areas which are used extensively in the practical work, particularly simulation, debugging and verification.
Aims
The module aims to give an overview of the processes involved in taking a concept onto a product chip. It also illustrates some of the choices available to an implementer. Finally, the practicals are intended to give some experience of the flow, the frustration and the satisfaction of making a working device.
Syllabus
The practical part of the course involves migrating the design of a moderately complex FSM into Verilog, integrating it with other parts of a system-on-chip, verifying that it operates correctly and demonstrating it working. The intention is to use a graphics drawing example design so that the final result can easily be seen on its own display.
The lectures are planned approximately as follows:
Introduction
The scale of the problem and what VLSI 'looks like', inside.
Verilog
Some revision plus some features you may not have met before.
Functional Simulation
Test harness construction and making things 'realistic'.
Debugging
What to look for and how to find it.
Tool flows
The sort of tools used to get source code into silicon and how to get the best from them.
Timing Simulation
Simulating big designs and getting sufficiently accurate results in days, not months.
Timing
Clocking, clock distribution and the perils of crossing between clock domains.
Technology
What every VLSI engineer needs to know about CMOS
Layout
Overcoming the crippling effects of reality on a nice, clean design.
Testing
Proving the device will work and then checking if it does when the silicon arrives.
Future
Silicon fabrication is still evolving rapidly. A look at some things which are going to make life (even) harder.
Teaching methods
Lectures
11
Laboratories
2 hours/week (1 hour timetabled, 1 hour independent work)
Feedback methods
Feedback is given orally in scheduled laboratories; lectures are intended to be active and discussion is encouraged.Annotated listings and diagrams will be returned to students.
Feedback as to whether a constructed (video) system operates correctly should be apparent from simulations during the work's progression and will definitely visible in the final realisation.
Study hours
- Assessment written exam (2 hours)
- Lectures (12 hours)
- Practical classes & workshops (12 hours)
Employability skills
- Analytical skills
- Innovation/creativity
- Problem solving
- Other
Learning outcomes
On successful completion of this unit, a student will be able to:
Learning outcomes are detailed on the COMP32212 course unit syllabus page on the School of Computer Science's website for current students.
Reading list
No reading list found for COMP32212.
Additional notes
Course unit materials
Links to course unit teaching materials can be found on the School of Computer Science website for current students.