A number of screenshots are available below. Certain features shown may only be availble when supported by the architecture of the connected device or emulator.
The main window shows the device's registers and memory complete with source code and disassembly.
The UI is flexible providing a number of ways to view the system memory and registers.
Memory and registers can be defined using a powerful Python-based expression language.
Support for additional peripherals such as FPGAs is built in.
Xilinx FPGA Bit-file Downloader
Additional low-level debugging controls.